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參數資料
| 型號： | THS14F03IPFBG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP48 |
| 封裝： | GREEN, PLASTIC, TQFP-48 |
| 文件頁數： | 9/24頁 |
| 文件大小： | 329K |
| 代理商： | THS14F03IPFBG4 |
THS14F01, THS14F03
14-BIT, 1 MSPS/ 3 MSPS, DSP COMPATIBLE, ANALOG-TO-DIGITAL CONVERTERS
WITH FIFO INTERNAL REFERENCE AND PGA
SLAS285 – JUNE 2000
17
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
DMA transfer and FIFO
The FIFO makes it possible to use the available interface bandwidth of the host processor more efficiently. The
following is a description based on the TMS320C6201 DSP from TI.
The TMS320C6201 memory interface has a limited bandwidth, for example 200MWPS at a clock rate of 200
MHz. The THS14F04x interface is asynchronous with a maximum speed of 300MWPS, which is approximately
7 clock cycles.
If the DSP uses the DMA controller to read data from the DSP, the following conditions exist:
D DMA bus arbitration:
16 clock cycles
D THS14F0x read access: 7 clock cycles
If, for example, 10 samples need to be read from the ADC without the FIFO, the memory interface will be
allocated for (10 + 7)
× 16 = 272 clock cycles in total.
BUSarb R
S
BUSarb R
S
BUSarb
R
S
BUSarb R
S
BUSarb
R
S
With a FIFO programmed to a 10 sample threshold, the memory interface will be allocated for 16 + 7
× 10 = 86
clock cycles in total.
BUSarb R
R
BUSarb R
R
BUS Available for Other Peripheral
driving the analog input
The THS14F01/3 ADCs have a fully differential input. A differential input is advantageous with respect to SNR,
SFDR, and THD performance because the signal peak-to-peak level is 50% of a comparable single-ended
input.
There are three basic input configurations:
D Fully differential
D Transformer coupled single-ended to differential
D Single-ended
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