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參數資料
| 型號： | THS14F03IPFBG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP48 |
| 封裝： | GREEN, PLASTIC, TQFP-48 |
| 文件頁數： | 7/24頁 |
| 文件大小： | 329K |
| 代理商： | THS14F03IPFBG4 |
THS14F01, THS14F03
14-BIT, 1 MSPS/ 3 MSPS, DSP COMPATIBLE, ANALOG-TO-DIGITAL CONVERTERS
WITH FIFO INTERNAL REFERENCE AND PGA
SLAS285 – JUNE 2000
15
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
Table 4. Control Register, Address 3, Read
BIT
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Function
PWD
REF
FOR
TM2
TM1
TM0
OFF
IP
FP
FC
F3
F2
F1
F0
Table 5. Control Register, Address 3, Write
BIT
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Function
PWD
REF
FOR
TM2
TM1
TM0
OFF
IP
FP
FC
F3
F2
F1
F0
Default
0
PWD:
Power down
0 = normal operation
1 = power down
REF:
Reference select
0 = internal reference
1 = external reference
FOR:
Output format
0 = straight binary
1 = 2s complement
TM2–0:
Test mode
000 = normal operation
001 = both inputs = REF–
010 = IN+ at Vref/2, IN– at REF–
011 = IN+ at REF+, IN– at REF–
100 = normal operation
101 = both inputs = REF+
110 = IN+ at REF–, IN– at Vref/2
111 = IN+ at REF–, IN– at REF+
OFF:
Offset correction
0 = enable
1 = disable
IP:
INT polarity
0 = low active
1 = high active
FP:
FIFO FOVL polarity 0 = low active
1 = high active
FC:
FIFO control
0 = disable FIFO
1 = enable FIFO
F3–0:
FIFO threshold
Sets the FIFO threshold for the INT signal in steps of 2 ranging from 0 to 30
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