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參數資料
| 型號： | TLC4545IDRG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8 |
| 封裝： | GREEN, PLASTIC, MS-012AA, SOIC-8 |
| 文件頁數： | 20/26頁 |
| 文件大小： | 652K |
| 代理商： | TLC4545IDRG4 |
TLC4541, TLC4545
SLAS293 DECEMBER 2001
3
www.ti.com
Terminal Functions
TLC4541 single channel unipolar ADCs
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
AIN
4
I
Analog input channel
CS
1
I
Chip select. A high-to-low transition on the CS input removes SDO from a high-impedance state within a
maximum delay time. If the TLC4541 is attached to a dedicated TMS320 DSP serial port using the FS input,
CS can be grounded.
FS
7
I
DSP frame sync input. Indication of a start of a serial data frame. A low-to-high transition removes SDO from
the high-impedance state and the MSB is presented. Tie this pin to VDD if not used.
GND
3
I
Ground return for the internal circuitry. Unless otherwise noted, all voltage measurements are with respect to
GND.
SDO
8
O
The 3-state serial data output for the A/D conversion result. SDO is kept in the high-impedance state when
CS is high. The output format is MSB first. Remaining data bits are presented on the rirsing edge of SCLK.
When FS is not active (FS = 1 at the falling edge of CS): The MSB is presented on the SDO pin on the falling
edge of CS after a maximum delay time. Data is valid on each falling edge of SCLK until all data is read.
When FS is active (FS = 0 at the falling edge of CS): The MSB is presented to the SDO output on the rising
edge of FS. Data is valid on the falling edge SCLK and changes on the rising edge SCLK (this is typically
used with an active FS from a DSP).
SDO returns to the high-impedance state after the 17th rising edge on SCLK. If a 17th SCLK cycle is not
presented, as is the case when using an SPI host, SDO returns to the high-impedance state on the rising
edge of CS.
SCLK
5
I
Serial clock. This terminal receives the serial SCLK from the host processor.
REF
2
I
External voltage reference input
VDD
6
I
Positive supply voltage
TLC4545 single channel pseudo-differential ADCs
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
AIN0 (+)
4
I
Positive analog input for the TLC4545.
AIN1 ()
5
I
Inverted analog input for the TLC4545.
CS
1
I
Chip select. A high-to-low transition on CS removes SDO from the high-impedance state within a maximum
delay time. The CS input can be connected to a DSP frame sync (FS) output when a dedicated TMS320 DSP
serial port is used.
GND
3
I
Ground return for the internal circuitry. Unless otherwise noted, all voltage measurements are with respect to
GND.
SDO
8
O
The 3-state serial data output for the A/D conversion result. SDO is kept in the high-impedance state when
CS is high and presents output data after the CS falling edge until the LSB is presented. The output format is
MSB first. The remaining data bits are presented on the rising edge of SCLK. Output data is valid on each
falling edge of SCLK until all data is read. SDO returns to the high-impedance state after the 17th rising edge
on SCLK. If a 17th SCLK cycle is not presented, as is the case when using an SPI host, SDO returns to the
high-impedance state on the rising edge of CS.
SCLK
7
I
Serial clock. This terminal receives the serial SCLK from the host processor.
REF
2
I
External voltage reference input
VDD
6
I
Positive supply voltage
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