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參數(shù)資料
| 型號： | TLC7628IN |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | DAC |
| 英文描述： | PARALLEL, 8 BITS INPUT LOADING, 0.1 us SETTLING TIME, 8-BIT DAC, PDIP20 |
| 封裝： | PLASTIC, DIP-20 |
| 文件頁數(shù)： | 8/13頁 |
| 文件大小： | 255K |
| 代理商： | TLC7628IN |
TLC7628C
DUAL 8BIT MULTIPLYING
SLAS063B APRIL 1989 REVISED MARCH 2007
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
operating characteristics over recommended ranges of operating free-air temperature and VDD,
VrefA = VrefB = 10 V, VOA and VOB at 0 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Linearity error
±1/2
LSB
Settling time (to 1/2 LSB)
See Note 1
100
ns
Gain error
See Note 2
Full range
±3
LSB
Gain error
See Note 2
25
°C
±2
LSB
AC feedthrough
REFA to OUTA
See Note 3
Full range
65
dB
AC feedthrough
REFB to OUTB
See Note 3
25
°C
75
dB
Temperature coefficient of gain
±0.0035 %FSR/°C
Propagation delay (from digital input to
90% of final analog output current)
See Note 4
80
ns
Channel-to-channel
REFA to OUTB
See Note 5
25
°C
80
dB
Channel-to-channel
isolation
REFB to OUTA
See Note 6
25
°C
80
dB
Digital-to-analog glitch impulse area
Measured for code transition from 00000000 to 11111111,
TA = 25°C
330
nV
s
Digital crosstalk
Measured for code transition from 00000000 to 11111111,
TA = 25°C
60
nV
s
Harmonic distortion
Vi = 6 V, f = 1 kHz, TA = 25°C
85
dB
NOTES:
1. OUTA, OUTB load = 100
, Cext = 13 pF; WR and CS at 0 V; DB0DB7 at 0 V to VDD or VDD to 0 V.
2. Gain error is measured using an internal feedback resistor. Nominal full scale range (FSR) = Vref 1 LSB. Both DAC latches are
loaded with 11111111.
3. Vref = 20 V peak-to-peak, 10-kHz sine wave
4. VrefA = VrefB = 10 V; OUTA/OUTB load = 100 , Cext = 13 pF; WR and CS at 0 V; DB0DB7 at 0 V to VDD or VDD to 0 V.
5. VrefA = 20 V peak-to-peak, 10-kHz sine wave; VrefB = 0
6. VrefB = 20 V peak-to-peak, 10-kHz sine wave; VrefA = 0
th(DAC)
th(CS)
tsu(CS)
tsu(DAC)
tw(WR)
th(D)
tsu(D)
Data In Stable
DB0 DB7
WR
CS
DACA/DACB
1.3 V
3.5 V
0.3 V
3.5 V
0.3 V
For all input signals, tr = tf = 5 ns (10% to 90% points).
1.3 V
Figure 1. Setup and Hold Times
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