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參數資料
| 型號： | TLC876MDWR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28 |
| 封裝： | SOP-28 |
| 文件頁數： | 21/22頁 |
| 文件大小： | 339K |
| 代理商： | TLC876MDWR |
TLC876M, TLC876I, TLC876C
10-BIT 20 MSPS PARALLEL OUTPUT CMOS
ANALOG-TO-DIGITAL CONVERTERS
SLAS140E – JULY 1997 – REVISED OCTOBER 2000
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
operating characteristics at AVDD = DVDD = 5 V, DRVDD = 3.3 V, VI(REFT) = 3.6 V, VI(REFB) = 1.6 V,
fCLK = 20 MSPS (unless otherwise noted)
timing requirements
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fconv
Maximum conversion rate (see Note 2)
20
MHz
td(o)
Delay time, output
CL = 20 pF
5
20
ns
td(pipe)
Delay time, pipeline, latency
3.5
Clock
cycles
td(A)
Delay time, aperture
4
ns
Aperture jitter
22
ps
tdis(DD)
Disable time, OE
↑ to Hi-Z
CL =20 pF
5
15
ns
ten(HL)
Enable time, OE
↓ to valid data
CL = 20 pF
5
15
ns
NOTE 2: The conversion rate can be a minimum of 10 kHz without degradation in specified performance.
PARAMETER MEASUREMENT INFORMATION
D0 – D9
Data N–4
Data N–3
Data N–2
Data N–1
Data N
tc
tw(CLKH)
tw(CLKL)
Sample N
Sample N+1
Sample N+2
AIN
CLK
td(o)
td(pipe)
td(A)
td(o)
Figure 1. Timing Diagram
tdis(DD)
ten(HL)
High Impedance
Active
OE
D0–D9
Figure 2. Output Enable to Data Output Timing Diagram
STBY
CLK
Output Data Valid
Figure 3. Standby Timing
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