- 您現在的位置：買賣IC網 > PDF目錄98250 > TLV1578IDAR (TEXAS INSTRUMENTS INC) 8-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO32 PDF資料下載
參數資料
| 型號： | TLV1578IDAR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 8-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO32 |
| 封裝： | GREEN, PLASTIC, TSSOP-32 |
| 文件頁數： | 30/33頁 |
| 文件大小： | 627K |
| 代理商： | TLV1578IDAR |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁當前第30頁第31頁第32頁第33頁
TLV1571, TLV1578
2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTERS
SLAS170D –MARCH 1999 – REVISED JULY 2000
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
detailed description (continued)
hardware configuration option
The TLV1571/TLV1578 can configure itself. This option is enabled when the WR pin is tied to ground and a
dummy RD signal is applied. The ADC is now fully configured. Zeros or default values are applied to both control
registers. The ADC is configured ideally for 3-V operation, which means the internal OSC is set at 10 MHz, single
channel input mode, and hardware start of conversion using CSTART.
ADC conversion modes
The TLV1571/ TLV1578 provides two conversion modes and two start of conversion modes. In single channel
input mode, a single channel is continuously sampled and converted. In sweep mode (only available for the
TLV1578), a predetermined set of channels is continuously sampled and converted. Table 1 explains these
modes in more detail.
Table 1. Conversion Modes
MODES
START OF
CONVER-
SION
OPERATION
COMMENT–SET BITS
CR0.D(2–0) FOR INPUT
Single
Channel
Input
CR0.D3 = 0
CR1.D7 = 0
Hardware
Start
(CSTART)
CR0.D7 = 0
Repeated conversions from a selected channel
CSTART falling edge to start sampling
CSTART rising edge to start conversion
If in INT mode, one INT pulse generated after each conversion
If in EOC mode, EOC will go high to low at start of conversion, and return high
at end of conversion.
CSTART rising edge must
be applied a minimum of
5 ns before or after CLK
rising edge.
Software
Start
CR0.D7 = 1
Repeated conversions from a selected channel
WR rising edge to start sampling initially. Thereafter, sampling occurs at the rising
edge of RD.
Conversion begins after 6 clocks after sampling has begun. Thereafter, if in INT
mode, one INT pulse is generated after each conversion
If in EOC mode, EOC will go high to low at start of conversion and return high at
end of conversion.
With external clock, WR
and RD rising edge must be
a minimum 5 ns before or
after CLK rising edge.
Channel
Sweep
CR0.D3 = 1
CR1.D7 = 0
Hardware
Start
(CSTART)
CR0.D7 = 0
One conversion per channel from a predetermined sequence of channels
CSTART falling edge to start sampling
CSTART rising edge to start conversion
If in INT mode, one INT pulse generated after each conversion
If in EOC mode, EOC will go high to low at start of conversion, and return high
at end of conversion.
CSTART rising edge must
be applied a minimum of
5 ns before or after CLK
rising edge.
Software
Start
CR0.D7 = 1
One conversion per channel from a sequence of channels
WR rising edge to start sampling
ADC proceeds to sample next channel at rising edge of RD. Conversion begins
after 6 clocks and lasts 10 clocks
If in INT mode, one INT pulse generated after each conversion
If in EOC mode, EOC will go high to low at start of conversion and return high at
end of conversion.
With external clock, WR
and RD rising edge must be
a minimum 5 ns before or
after CLK rising edge.
Single channel input mode repeatedly samples and converts from the channel until WR is applied.
相關PDF資料 |
PDF描述 |
|---|---|
| TLV2541IDR | 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8 |
| TLV2541CDGKR | 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8 |
| TLV2545CDGK | 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8 |
| TLV2545CDGKG4 | 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8 |
| TLV2542CDGK | 2-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| TLV1701AIDBVR | 功能描述:Comparator General Purpose Open Collector SOT-23-5 制造商:texas instruments 系列:- 包裝:剪切帶（CT） 零件狀態:有效 類型:通用 元件數:1 輸出類型:開路集電極 電壓 - 電源，單/雙（±）:2.2 V ~ 36 V，±1.1 V ~ 18 V 電壓 - 輸入失調（最大值）:3.5mV 電流 - 輸入偏置（最大值）:15nA 電流 - 輸出（典型值）:20mA 電流 - 靜態（最大值）:75μA CMRR，PSRR（典型值）:- 傳播延遲（最大值）:560ns 滯后:- 工作溫度:-40°C ~ 125°C 封裝/外殼:SC-74A，SOT-753 安裝類型:表面貼裝 供應商器件封裝:SOT-23-5 標準包裝:1 |
| TLV1701AIDBVT | 功能描述:Comparator General Purpose Open Collector SOT-23-5 制造商:texas instruments 系列:- 包裝:剪切帶（CT） 零件狀態:有效 類型:通用 元件數:1 輸出類型:開路集電極 電壓 - 電源，單/雙（±）:2.2 V ~ 36 V，±1.1 V ~ 18 V 電壓 - 輸入失調（最大值）:3.5mV 電流 - 輸入偏置（最大值）:15nA 電流 - 輸出（典型值）:20mA 電流 - 靜態（最大值）:75μA CMRR，PSRR（典型值）:- 傳播延遲（最大值）:560ns 滯后:- 工作溫度:-40°C ~ 125°C 封裝/外殼:SC-74A，SOT-753 安裝類型:表面貼裝 供應商器件封裝:SOT-23-5 標準包裝:1 |
| TLV1701AIDCKR | 功能描述:Comparator General Purpose Open Collector SC-70-5 制造商:texas instruments 系列:- 包裝:剪切帶（CT） 零件狀態:有效 類型:通用 元件數:1 輸出類型:開路集電極 電壓 - 電源，單/雙（±）:2.2 V ~ 36 V，±1.1 V ~ 18 V 電壓 - 輸入失調（最大值）:3.5mV 電流 - 輸入偏置（最大值）:15nA 電流 - 輸出（典型值）:20mA 電流 - 靜態（最大值）:75μA CMRR，PSRR（典型值）:- 傳播延遲（最大值）:560ns 滯后:- 工作溫度:-40°C ~ 125°C 封裝/外殼:5-TSSOP，SC-70-5，SOT-353 安裝類型:表面貼裝 供應商器件封裝:SC-70-5 標準包裝:1 |
| TLV1701AIDCKT | 功能描述:Comparator General Purpose Open Collector SC-70-5 制造商:texas instruments 系列:- 包裝:剪切帶（CT） 零件狀態:有效 類型:通用 元件數:1 輸出類型:開路集電極 電壓 - 電源，單/雙（±）:2.2 V ~ 36 V，±1.1 V ~ 18 V 電壓 - 輸入失調（最大值）:3.5mV 電流 - 輸入偏置（最大值）:15nA 電流 - 輸出（典型值）:20mA 電流 - 靜態（最大值）:75μA CMRR，PSRR（典型值）:- 傳播延遲（最大值）:560ns 滯后:- 工作溫度:-40°C ~ 125°C 封裝/外殼:5-TSSOP，SC-70-5，SOT-353 安裝類型:表面貼裝 供應商器件封裝:SC-70-5 標準包裝:1 |
| TLV1701AIDRLT | 功能描述:Comparator General Purpose Open Collector SOT-5 制造商:texas instruments 系列:- 包裝:剪切帶（CT） 零件狀態:有效 類型:通用 元件數:1 輸出類型:開路集電極 電壓 - 電源，單/雙（±）:2.2 V ~ 36 V，±1.1 V ~ 18 V 電壓 - 輸入失調（最大值）:3.5mV 電流 - 輸入偏置（最大值）:15nA 電流 - 輸出（典型值）:20mA 電流 - 靜態（最大值）:75μA CMRR，PSRR（典型值）:- 傳播延遲（最大值）:560ns 滯后:- 工作溫度:-40°C ~ 125°C 封裝/外殼:SOT-553 安裝類型:表面貼裝 供應商器件封裝:SOT-5 標準包裝:1 |
發布緊急采購，3分鐘左右您將得到回復。