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參數資料
| 型號： | TLV2556MPWREPG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 11-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20 |
| 封裝： | GREEN, PLASTIC, TSSOP-20 |
| 文件頁數： | 22/37頁 |
| 文件大小： | 705K |
| 代理商： | TLV2556MPWREPG4 |
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01: 8-bit output length
X0: 12-bit output length
11: 16-bit output length (default)
0: MSB out first (default)
1: LSB out first
0: Unipolar binary (default)
1: Bipolar 2s complement
00: Internal 4.096 reference
01: Internal 2.048 reference
11: External reference (default)
0: Pin 19 output EOC (default)
1: Pin 19 output Int
0: Normal mode
(CFGR1 needs to be programmed)
1: Default mode enabled
(D[3:0] of CFGR1 and D[3:1] of
CFGR2 set to default)
SDI D[7:4]
Binary,
HEX
COMMAND
0000b
0001b
0010b
0011b
0100b
0101b
0110b
0111b
1000b
1001b
1010b
1011b
1100b
1101b
1110b
1111b
0h
1h
2h
3h
4h
5h
6h
7h
8h
9h
Ah
Bh
Ch
Dh
Eh
Fh
SELECT analog input channel 0
SELECT analog input channel 1
SELECT analog input channel 2
SELECT analog input channel 3
SELECT analog input channel 4
SELECT analog input channel 5
SELECT analog input channel 6
SELECT analog input channel 7
SELECT analog input channel 8
SELECT analog input channel 9
SELECT analog input channel 10
SELECT TEST,
Voltage = (VREF+ + VREF)/2
SELECT TEST, Voltage = REFM
SELECT TEST, Voltage = REFP
SW POWERDOWN (analog + reference)
ACCESS CFGR2
CONFIGURATION
CFGR1
SDI
D[3:0]
D[3:2]
D1
D0
CONFIGURATION
CFGR2
SDI
D[3:0]
D[3:2]
D1
D0
Data Input – Address/Command Bits
Data Output Length
www.ti.com ................................................................................................................................................... SLAS598A – NOVEMBER 2008 – REVISED JULY 2009
Table 2. Command Set (CMR) and Configuration
The four MSBs (D7–D4) of the input data register are the address or command. These bits can be used to
address one of the 11 input channels, select one of three reference-test voltages, activate the software
power-down mode, or access the second configuration register, CFGR2. All address/command bits affect the
current conversion, which is the conversion that immediately follows the current I/O cycle. They also allow
access to CFGR1 except for command 1111b, which allows access to CFGR2.
CFGR1 bits (D3 and D2) of the data register select the output data length. The data-length selection is valid for
the current I/O cycle (the cycle in which the data is read). The data-length selection, being valid for the current
I/O cycle, allows device start-up without losing I/O synchronization. A data length of 8, 12, or 16 bits can be
selected. Since the converter has 12-bit resolution, a data length of 12 bits is suggested.
With D3 and D2 set to 00 or 10, the device is in the 12-bit data-length mode and the result of the current
conversion is output as a 12-bit serial data stream during the next I/O cycle. The current I/O cycle must be
exactly 12 bits long for proper synchronization, even when this means corrupting the output data from a previous
conversion. The current conversion is started immediately after the twelfth falling edge of the current I/O cycle.
Copyright 2008–2009, Texas Instruments Incorporated
29
Product Folder Link(s): TLV2556-EP
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