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參數(shù)資料
| 型號： | TLV2556MPWREPG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 11-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20 |
| 封裝： | GREEN, PLASTIC, TSSOP-20 |
| 文件頁數(shù)： | 25/37頁 |
| 文件大小： | 705K |
| 代理商： | TLV2556MPWREPG4 |
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C1
0.1
F
Decoupling Cap
C2
10
F
Int Reference
Compensation Cap
GND
Analog
Supply
Sample
50 pF
CDAC
Convert
REF+
REF
Internal
Reference
VCC
S1, S2:
Closed = Internal Reference Used
Opened = External Reference Used
C2 and Grounding REF Are Required
When Either 4.096 V or 2.048 Internal
Reference Is Used
S1
S2
INT/EOC Output
Chip-Select Input (CS)
www.ti.com ................................................................................................................................................... SLAS598A – NOVEMBER 2008 – REVISED JULY 2009
Figure 54. Reference Block
Pin 19 outputs the status of the ADC conversion. When programmed as EOC, the output indicates the beginning
and the end of conversion. In the reset state, EOC is always high. During the sampling period (beginning after
the fourth falling edge of the I/O CLOCK sequence), EOC remains high until the internal sampling switch of the
converter is safely opened. The opening of the sampling switch occurs after the eighth, twelfth, or sixteenth I/O
CLOCK falling edge, depending on the data-length selection in the input data register. After the EOC signal goes
low, the analog input signal can be changed without affecting the conversion result.
The EOC signal goes high again after the conversion is completed and the conversion result is latched into the
output data register. The rising edge of EOC returns the converter to a reset state and a new I/O cycle begins.
On the rising edge of EOC, the first bit of the current conversion result is on DATA OUT when CS is low. When
CS is toggled between conversions, the first bit of the current conversion result occurs on DATA OUT at the
falling edge of CS.
When programmed as INT, the output indicates that the conversion is completed and the output data is ready to
be read. In the reset state, INT is always high. INT is high during the sampling period and until the conversion is
complete. After the conversion is finished and the output data is latched, INT goes low and remains low until it is
cleared by the host. When CS is held low, the MSB (or LSB) of the conversion result is presented on DATA OUT
on the falling edge of INT. A rising I/O CLOCK edge clears the interrupt.
CS enables and disables the device. During normal operation, CS should be low. Although the use of CS is not
necessary to synchronize a data transfer, it can be brought high between conversions to coordinate the data
transfer of several devices sharing the same bus.
When CS is brought high, the serial-data output is immediately brought to the high-impedance state, releasing its
output data line to other devices that may share it. After an internally generated debounce time, I/O CLOCK is
inhibited, thus preventing any further change in the internal state.
When CS is subsequently brought low again, the device is reset. CS must be held low for an internal debounce
time before the reset operation takes effect. After CS is debounced low, I/O CLOCK must remain inactive (low)
for a minimum time before a new I/O cycle can start.
Copyright 2008–2009, Texas Instruments Incorporated
31
Product Folder Link(s): TLV2556-EP
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