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參數資料
型號: TLV320AIC27TPFB
廠商: TEXAS INSTRUMENTS INC
元件分類: 消費家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP48
封裝: PLASTIC, TQFP-48
文件頁數: 4/54頁
文件大小: 732K
代理商: TLV320AIC27TPFB
TLV320AIC27
STEREO AUDIO CODEC
SLAS253A – MARCH 2000 – REVISED SEPTEMBER 2000
12
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
master/slave ID0/1 support
TLV320AIC27 supports operation as either a master or a slave codec. Configuring the device as master or slave
is accomplished by tying together the CID pins CID0 and CID1 (pins 45 and 46 ).
Fundamentally, a device identified as a master (ID = 00) produces BITCLK as an output, whereas a slave (any
ID but 00) must be provided with BITCLK as an input. The obvious implication is that if the master device on
an ac link is disabled, the slave devices cannot function.
The AC’97 Revision 2.1 specification defines the CID pins as having inverting sense and being provided with
internal weak pull ups. Therefore, if no connections are made to the CID0/1 pins, then these pins pull hi and
an ID = 00 (or master) is selected. External connections to ground select other IDs.
Table 4. ID Selection
PIN 45 CID0
PIN 46 CID1
ID SELECTED
MASTER OR
SLAVE
BITCLK
NC
00
Master
Output
NC
Ground
01
Slave
Input
Ground
NC
10
Slave
Input
Ground
11
Slave
Input
The TLV320AIC27 supports the AMAP function, whereby selection of an ID automatically maps the data from
the interface onto the PCM DACs.
Table 5. Default Slot to DAC Mappings Based on Codec ID
AC-LINK FRAME DATA
USED FOR DACs
CODEC ID
PCM LEFT DAC
USES DATA FROM
SLOT NUMBER
PCM RIGHT DAC
USES DATA FROM
SLOT NUMBER
COMMENTS
00
3
4
Original definition (master)
01
3
4
Original definition (docking)
10
7
8
Left/right surround channels
11
6
9
Center/LFE channels
The codec ID is available to the controller via register 28h and C3, bits D15 and D14
The previous automatic mapping of data to slots is extended when the device is operated in the alternative
modes selectable via the mode pins. In these cases the selection of which data slots are mapped onto internal
DACs or I2S outputs is accomplished as shown in Table 6. Note that I2S enable bit must be set.
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