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參數資料
| 型號： | TLV320AIC27TPFB |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封裝： | PLASTIC, TQFP-48 |
| 文件頁數： | 54/54頁 |
| 文件大小： | 732K |
| 代理商： | TLV320AIC27TPFB |
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TLV320AIC27
STEREO AUDIO CODEC
SLAS253A – MARCH 2000 – REVISED SEPTEMBER 2000
9
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over operating temperature range, AVDD = 5 V, DVDD = 3.3 V, GND = 0 V
(unless otherwise noted) (continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Mixer-Circuit Specifications (AVDD = 3.3 V) 48 kHz sampling
SNR CD path A-weighted (see Note 1)
92
dB
SNR other paths A-weighted (see Note 1)
92
dB
Maximum input voltage
0.66
Vrms
Maximum output voltage on LINEOUT
0.66
Vrms
THD
0-dB voltage input
74
90
dB
Frequency response (
±1 dB)
20
20000
Hz
Input impedance (CD inputs)
At any gain
15
k
Input impedance (other mixer inputs)
At maximum gain
20
k
Input impedance (other mixer inputs)
At 0-dB gain
100
k
Input impedance mic inputs
At any gain
30
k
PSRR
20 Hz to 20 kHz
40
dB
Clock-Frequency Range
Crystal clock
24.576
MHz
BIT_CLK frequency
12.288
MHz
SYNC frequency
48.0
kHz
NOTE 1: SNR is the ratio of 0-dB signal output level to the output level with no signal, measured A-weighted over a 20 Hz to 20 kHz bandwidth.
detailed description
3D stereo enhancement
This device contains a stereo-enhancement circuit, designed to optimize the listening experience when the
device is used in a typical PC-operating environment (that is, with a pair of speakers placed either side of the
monitor with little spatial separation). This circuit creates a differential signal by subtracting left and right channel
playback data, then filters this difference signal using low-pass and high-pass filters whose time constants are
set using external capacitors connected to the CX3D pins 33 and 34. Typical values of 100 nF and 47 nF set
high-pass and low-pass poles at about 100 Hz and 1 kHz respectively. This frequency band corresponds to the
range over which the ear is most sensitive to directional effects.
The filtered difference signal is gain-adjusted by an amount set using the four-bit value written to register 22h
bits 3 to 0. Value 0h is disabled, and value Fh is maximum effect. A typical value of 8h is optimum. The user
interface most typically uses a slider type of control to allow the user to adjust the level of enhancement to suit
the program material. Bit D13 3D in register 20h is the overall 3D-enable bit. The capability register 00h reads
back the value 11000 in bits D14 to D10. This corresponds to decimal 24, which is registered with Intel as Texas
Instruments Stereo Enhancement.
Note that the external capacitors setting the filtering poles applied to the difference signal can be adjusted in
value, or even replaced with a direct connection between the pins. When such adjustments are made, the
amount of difference signal fed back into the main signal paths can be significant. This can cause large signals
which may limit, distort, or overdrive signal paths or speakers. Adjust these values carefully to select the desired
acoustic effect.
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