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參數資料
| 型號： | TLV320DAC32IRHBTG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | DAC |
| 英文描述： | SERIAL INPUT LOADING, DAC WITH PROGRAMMABLE PLL, PQCC32 |
| 封裝： | 5 X 5 MM, GREEN, PLASTIC, QFN-32 |
| 文件頁數： | 24/69頁 |
| 文件大小： | 1242K |
| 代理商： | TLV320DAC32IRHBTG4 |
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LB1
RB2
Atten
LB2
L
R
TOLEFTCHANNEL
TO RIGHT CHANNEL
TOLEFTCHANNEL
TORIGHTCHANNEL
DIGITAL INTERPOLATION FILTER
DELTA-SIGMA AUDIO DAC
SLAS506B – NOVEMBER 2006 – REVISED DECEMBER 2008........................................................................................................................................ www.ti.com
Figure 33. Architecture of the Digital Audio Processing When 3-D Effects are Enabled
It is recommended that the digital effects filters should be disabled while the filter coefficients are being modified.
Since updating all 5 digital coefficients using the I2C control port can take more than 1 LRCLK cycle, it is
therefore possible that a filter using partially updated coefficients may actually implement an unstable filter and
lead to an oscillation or objectionable audio output. By first disabling the filters, then changing the all of the
coefficients as needed, and then re-enabling the filters, these types of effects can be entirely avoided.
The digital interpolation filter upsamples the output of the digital audio processing block by the required
oversampling ratio before data is provided to the digital delta-sigma modulator and analog reconstruction filter
stages. The filter provides a linear phase output with a group delay of 21/Fs. In addition, programmable digital
interpolation filtering is included to provide enhanced image filtering and reduce signal images caused by the
upsampling process that are below 20-kHz. For example, upsampling an 8-kHz signal produces signal images at
multiples of 8-kHz (i.e., 8-kHz, 16-kHz, 24-kHz, etc). The images at 8-kHz and 16-kHz are below 20-kHz and still
audible to the listener; therefore, they must be filtered heavily to maintain a good quality output. The interpolation
filter in this device is designed to maintain at least 65-dB rejection of images that land below 7.455 Fs. In order to
utilize the programmable interpolation capability, the Fsref should be programmed to a higher rate (restricted to
be in the range of 39-kHz to 53-kHz when the PLL is in use), and the actual Fs is set using the NDAC divider.
For example, if Fs = 8-kHz is required, then Fsref can be set to 48-kHz, and the DAC Fs set to Fsref/6. This
ensures that all images of the 8-kHz data are sufficiently attenuated well beyond a 20-kHz audible frequency
range.
The stereo audio DAC incorporates a third order multi-bit delta-sigma modulator followed by an analog
reconstruction filter. The DAC provides high-resolution, low-noise performance, using oversampling and noise
shaping techniques. The analog reconstruction filter design consists of a 6 tap analog FIR filter followed by a
continuous time RC filter. The analog FIR operates at a rate of 128 x Fsref (6.144 MHz when Fsref = 48-kHz,
5.6448-MHz when Fsref = 44.1-kHz). Note that the DAC analog performance may be degraded by excessive
clock jitter on the MCLK input. Therefore, care must be taken in the system design to keep jitter on this clock to a
minimum.
30
Copyright 2006–2008, Texas Instruments Incorporated
Product Folder Link(s): TLV320DAC32
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