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參數資料
| 型號： | TLV5535IPWRQ1 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28 |
| 封裝： | PLASTIC, TSSOP-28 |
| 文件頁數： | 10/35頁 |
| 文件大小： | 659K |
| 代理商： | TLV5535IPWRQ1 |
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TLV5535Q1
8BIT, 35 MSPS, LOW POWER ANALOGTODIGITAL CONVERTER
SGLS230A JANUARY 2004 REVISED JUNE 2008
18
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLE OF OPERATION
digital inputs (continued)
The CLK signal at high frequencies should be considered as an analog input. Overshoot/undershoot should be
minimized by proper termination of the signal close to the TLV5535. An important cause of performance
degradation for a high-speed ADC is clock jitter. Clock jitter causes uncertainty in the sampling instant of the
ADC, in addition to the inherent uncertainty on the sampling instant caused by the part itself, as specified by
its aperture jitter. There is a theoretical relationship between the frequency (f) and resolution (2N) of a signal
that needs to be sampled and the maximum amount of aperture error dtmax that is tolerable. The following
formula shows the relation:
dtmax + 1 B p f2
N
)1
As an example, for an 8-bit converter with a 15-MHz input, the jitter needs to be kept < 41 pF in order not to have
changes in the LSB of the ADC output due to the total aperture error.
digital outputs
The output of the TLV5535 is standard binary code. Capacitive loading on the output should be kept as low as
possible (a maximum loading of 10 pF is recommended) to provide the best performance. Higher output loading
causes higher dynamic output currents and can increase noise coupling into the analog front end of the device.
To drive higher loads, the use of an output buffer is recommended.
When clocking output data from the TLV5535, it is important to observe its timing relation to CLK. The pipeline
ADC delay is 4.5 clock cycles to which the maximum output propagation delay is added. See Note 6 in the
specification section for more details.
layout, decoupling and grounding rules
It is necessary for any PCB using the TLV5535 to have proper grounding and layout to achieve the stated
performance. Separate analog and digital ground planes that are spliced underneath the device are advisable.
The TLV5535 has digital and analog terminals on opposite sides of the package to make proper grounding
easier. Since there is no internal connection between the analog and digital grounds, they have to be joined on
the PCB. Joining the digital and analog grounds at a point in close proximity to the TLV5535 is advised.
As for power supplies, separate analog and digital supply terminals are provided on the device (AVDD/DVDD).
The supply to the digital output drivers is kept separate also (DRVDD). Lowering the voltage on this supply from
the nominal 3.3 V to 3 V improves performance because of the lower switching noise caused by the output
buffers.
Due to the high sampling rate and switched-capacitor architecture, the TLV5535 generates transients on the
supply and reference lines. Proper decoupling of these lines is essential. Decoupling as shown in the schematic
of the TLV5535 EVM is recommended.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| TLV5535PW | 制造商:TI 制造商全稱:Texas Instruments 功能描述:8-BIT, 35 MSPS, LOW-POWER ANALOG-TO-DIGITAL CONVERTER |
| TLV5535-Q1 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:8-BIT, 35 MSPS, LOW-POWER ANALOG-TO-DIGITAL CONVERTER |
| TLV5580 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:8-BIT, 80 MSPS LOW-POWER A/D CONVERTER |
| TLV5580CDW | 功能描述:模數轉換器 - ADC 8 BIT, 80 MSPS LOW-POWER ADC RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| TLV5580CDWG4 | 功能描述:模數轉換器 - ADC 8Bit 80MSPS 1-Ch High Ch Band Lo-Pwr RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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