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參數(shù)資料
| 型號： | TLV5535IPWRQ1 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28 |
| 封裝： | PLASTIC, TSSOP-28 |
| 文件頁數(shù)： | 32/35頁 |
| 文件大小： | 659K |
| 代理商： | TLV5535IPWRQ1 |
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TLV5535Q1
8BIT, 35 MSPS, LOW POWER ANALOGTODIGITAL CONVERTER
SGLS230A JANUARY 2004 REVISED JUNE 2008
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating conditions, fCLK = 35 MSPS, external
voltage references (unless otherwise noted) (continued)
logic outputs
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOH
High-level output voltage
AVDD = DVDD = DRVDD = 3 V at IOH = 50 A,
Digital output forced high
2.8
V
VOL
Low-level output voltage
AVDD = DVDD = DRVDD = 3.6 V at IOL = 50 A,
Digital output forced low
0.1
V
CO
Output capacitance
5
pF
IOZH
High-impedance state output current to
high level
AVDD = DVDD = DRVDD = 3.6 V
10
A
IOZL
High-impedance state output current to
low level
AVDD = DVDD = DRVDD = 3.6 V
10
A
dc accuracy
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Integral nonlinearity (INL), best-fit
Internal references (see Note 1)
TA = 25°C
1.5
±0.7
1.5
LSB
Integral nonlinearity (INL), best-fit
Internal references (see Note 1)
TA = 40°C to 85°C
2.4
±0.7
2.4
LSB
Differential nonlinearity (DNL)
Internal references (see Note 2),
TA = 40°C to 85°C
1
±0.6
1.3
LSB
Zero error
AVDD = DVDD = 3.3 V, DRVDD = 3 V,
5
%FS
Full-scale error
AVDD = DVDD = 3.3 V, DRVDD = 3 V,
Internal references (see Note 3)
5
%FS
NOTES:
1. Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero to full scale. The point used as zero
occurs 1/2 LSB before the first code transition. The full-scale point is defined as a level 1/2 LSB beyond the last code transition. The
deviation is measured from the center of each particular code to the true straight line between these two endpoints.
2. An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Therefore this measure
indicates how uniform the transfer function step sizes are. The ideal step size is defined here as the step size for the device under
test [i.e., (last transition level first transition level)
÷ (2n 2)]. Using this definition for DNL separates the effects of gain and offset
error. A minimum DNL better than 1 LSB ensures no missing codes.
3. Zero error is defined as the difference in analog input voltage between the ideal voltage and the actual voltage that switches
the ADC output from code 0 to code 1. The ideal voltage level is determined by adding the voltage corresponding to 1/2 LSB to the
bottom reference level. The voltage corresponding to 1 LSB is found from the difference of top and bottom references divided by
the number of ADC output levels (256).
Full-scale error is defined as the difference in analog input voltage – between the ideal voltage and the actual voltage – that switches
the ADC output from code 254 to code 255. The ideal voltage level is determined by subtracting the voltage corresponding to 1.5
LSB from the top reference level. The voltage corresponding to 1 LSB is found from the difference of top and bottom references
divided by the number of ADC output levels (256).
analog input
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CI
Input capacitance
4
pF
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| TLV5580CDW | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 8 BIT, 80 MSPS LOW-POWER ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| TLV5580CDWG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 8Bit 80MSPS 1-Ch High Ch Band Lo-Pwr RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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