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| 型號： | TLV5535IPWRQ1 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28 |
| 封裝： | PLASTIC, TSSOP-28 |
| 文件頁數(shù)： | 34/35頁 |
| 文件大?。?/td> | 659K |
| 代理商： | TLV5535IPWRQ1 |
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TLV5535Q1
8BIT, 35 MSPS, LOW POWER ANALOGTODIGITAL CONVERTER
SGLS230A JANUARY 2004 REVISED JUNE 2008
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating conditions, fCLK = 35 MSPS, external
voltage references (unless otherwise noted) (continued)
timing requirements
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fCLK
Maximum conversion rate
35
MHz
fCLK
Minimum conversion rate
10
kHz
td(o)
Output delay time (see Figure 1)
CL = 10 pF,
See Notes 5 and 6
9
ns
th(o)
Output hold time
CL = 2 pF,
See Note 5
2
ns
td(pipe)
Pipeline delay time (latency)
See Note 6
4.5
CLK
cycles
td(a)
Aperture delay time
3
ns
tj(a)
Aperture jitter
See Note 5
1.5
ps, rms
tdis
Disable time, OE rising to Hi-Z
See Note 5
5
8
ns
ten
Enable time, OE falling to valid data
5
8
ns
NOTES:
5. Output timing td(o) is measured from the 1.5 V level of the CLK input falling edge to the 10%/90% level of the digital output. The digital
output load is not higher than 10 pF.
Output hold time th(o) is measured from the 1.5 V level of the CLK input falling edge to the 10%/90% level of the digital output. The
digital output is load is not less than 2 pF.
Aperture delay td(A) is measured from the 1.5 V level of the CLK input to the actual sampling instant.
The OE signal is asynchronous.
OE timing tdis is measured from the VIH(MIN) level of OE to the high-impedance state of the output data. The digital output load is
not higher than 10 pF.
OE timing ten is measured from the VIL(MAX) level of OE to the instant when the output data reaches VOH(min) or VOL(max) output
levels. The digital output load is not higher than 10 pF.
6. The number of clock cycles between conversion initiation on an input sample and the corresponding output data being made
available from the ADC pipeline. Once the data pipeline is full, new valid output data is provided on every clock cycle. In order to
know when data is stable on the output pins, the output delay time td(o) (i.e., the delay time through the digital output buffers) needs
to be added to the pipeline latency. Note that since the max td(o) is more than 1/2 clock period at 35 MHz, data cannot be reliably
clocked in on a rising edge of CLK at this speed. The falling edge should be used.
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