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參數(shù)資料
| 型號： | TLV5618AMDREPG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | DAC |
| 英文描述： | SERIAL INPUT LOADING, 3 us SETTLING TIME, 12-BIT DAC, PDSO8 |
| 封裝： | GREEN, SOIC-8 |
| 文件頁數(shù)： | 13/17頁 |
| 文件大小： | 389K |
| 代理商： | TLV5618AMDREPG4 |
TLV5618AEP
2.7V TO 5.5V LOW POWER DUAL 12BIT
DIGITALTOANALOG CONVERTER WITH POWER DOWN
SGLS214 OCTOBER 2003
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating conditions (unless otherwise noted)
(continued)
reference input
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VI
Input voltage range
0
VDD1.5
V
RI
Input resistance
10
M
CI
Input capacitance
5
pF
Reference input bandwidth
REF = 0.2 Vpp + 1.024 V dc
Fast
1.3
MHz
Reference input bandwidth
REF = 0.2 Vpp + 1.024 V dc
Slow
525
kHz
Reference feedthrough
REF = 1 Vpp at 1 kHz + 1.024 V dc (see Note 10)
80
dB
NOTE 10: Reference feedthrough is measured at the DAC output with an input code = 0x000.
digital inputs
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IIH
High-level digital input current
VI = VDD
1
A
IIL
Low-level digital input current
VI = 0 V
1
A
Ci
Input capacitance
8
pF
analog output dynamic performance
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ts(FS)
Output settling time, full scale
RL = 10 k,CL = 100 pF, See Note 11
Fast
1
3
s
ts(FS)
Output settling time, full scale
RL = 10 k,CL = 100 pF, See Note 11
Slow
3
10
s
ts(CC)
Output settling time, code to code
RL = 10 k,CL = 100 pF, See Note 12
Fast
1
s
ts(CC)
Output settling time, code to code
RL = 10 k,CL = 100 pF, See Note 12
Slow
2
s
SR
Slew rate
RL = 10 k,CL = 100 pF, See Note 13
Fast
3
V/ s
SR
Slew rate
RL = 10 k,CL = 100 pF, See Note 13
Slow
0.5
V/
s
Glitch energy
DIN = 0 to 1,
FCLK = 100 kHz, CS = VDD
5
nVs
SNR
Signal-to-noise ratio
76
SINAD
Signal-to-noise + distortion
fs = 102 kSPS, fout = 1 kHz, RL = 10 k,
68
dB
THD
Total harmonic distortion
fs = 102 kSPS, fout = 1 kHz, RL = 10 k,
CL = 100 pF
68
dB
SFDR
Spurious free dynamic range
CL = 100 pF
72
NOTES: 11. Settling time is the time for the output signal to remain within
±0.5 LSB of the final measured value for a digital input code change
of 0x020 to 0xFDF and 0xFDF to 0x020 respectively. Not tested, assured by design.
12. Settling time is the time for the output signal to remain within
± 0.5 LSB of the final measured value for a digital input code change
of one count. Not tested, assured by design.
13. Slew rate determines the time it takes for a change of the DAC output from 10% to 90% of full-scale voltage.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TLV5618AMFK | 制造商:TI 制造商全稱:Texas Instruments 功能描述:2.7-V TO 5.5-V LOW-POWER DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN |
| TLV5618AMFKB | 制造商:Texas Instruments 功能描述:12-BIT, 2.5 US DUAL DAC, SERIAL INPUT |
| TLV5618AMJG | 制造商:Texas Instruments 功能描述:DAC 2-CH Resistor-String 12-bit 8-Pin CDIP Tube |
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| TLV5618AQD | 功能描述:數(shù)模轉(zhuǎn)換器- DAC Dual 12bit DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
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