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參數資料
| 型號： | TLV5618AMDREPG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | DAC |
| 英文描述： | SERIAL INPUT LOADING, 3 us SETTLING TIME, 12-BIT DAC, PDSO8 |
| 封裝： | GREEN, SOIC-8 |
| 文件頁數： | 2/17頁 |
| 文件大小： | 389K |
| 代理商： | TLV5618AMDREPG4 |
TLV5618AEP
2.7V TO 5.5V LOW POWER DUAL 12BIT
DIGITALTOANALOG CONVERTER WITH POWER DOWN
SGLS214 OCTOBER 2003
10
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
general function
The TLV5618A is a dual 12-bit, single-supply DAC, based on a resistor-string architecture. It consists of a serial
interface, a speed and power down control logic, a resistor string, and a rail-to-rail output buffer.
The output voltage (full scale determined by the reference) is given by:
2REF
CODE
2n
[V]
Where REF is the reference voltage and CODE is the digital input value within the range of 010 to 2n1, where
n=12 (bits). The 16-bit data word, consisting of control bits and the new DAC value, is illustrated in the data
format section. A power-on reset initially resets the internal latches to a defined state (all bits zero).
serial interface
A falling edge of CS starts shifting the data bit-per-bit (starting with the MSB) to the internal register on the falling
edges of SCLK. After 16 bits have been transferred or CS rises, the content of the shift register is moved to the
target latches (DAC A, DAC B, BUFFER, CONTROL), depending on the control bits within the data word.
Figure 12 shows examples of how to connect the TLV5618A to TMS320, SPI, and Microwire.
TMS320
DSP FSX
CLKX
DX
TLV5618A
SCLK
DIN
CS
SPI
I/O
SCK
MOSI
TLV5618A
SCLK
DIN
CS
Microwire
I/O
SK
SO
TLV5618A
SCLK
DIN
CS
Figure 12. Three-Wire Interface
Notes on SPI and Microwire: Before the controller starts the data transfer, the software has to generate a falling
edge on the pin connected to CS. If the word width is 8 bits (SPI and Microwire) two write operations must be
performed to program the TLV5618A. After the write operation(s), the holding registers or the control register
are updated automatically on the next positive clock edge following the 16th falling clock edge.
serial clock frequency and update rate
The maximum serial clock frequency is given by:
f
sclkmax +
1
t
whmin )
t
wlmin
+ 20 MHz
The maximum update rate is:
f
updatemax +
1
16 t
whmin )
t
wlmin
+ 1.25 MHz
Note that the maximum update rate is just a theoretical value for the serial interface, as the settling time of the
TLV5618A should also be considered.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| TLV5618AMFK | 制造商:TI 制造商全稱:Texas Instruments 功能描述:2.7-V TO 5.5-V LOW-POWER DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN |
| TLV5618AMFKB | 制造商:Texas Instruments 功能描述:12-BIT, 2.5 US DUAL DAC, SERIAL INPUT |
| TLV5618AMJG | 制造商:Texas Instruments 功能描述:DAC 2-CH Resistor-String 12-bit 8-Pin CDIP Tube |
| TLV5618AMJGB | 制造商:Texas Instruments 功能描述:DAC 2-CH Resistor-String 12-bit 8-Pin CDIP Tube |
| TLV5618AQD | 功能描述:數模轉換器- DAC Dual 12bit DAC RoHS:否 制造商:Texas Instruments 轉換器數量:1 DAC 輸出端數量:1 轉換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩定時間:1 us 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
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