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參數資料
| 型號： | TLV5633IPWRG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | DAC |
| 英文描述： | PARALLEL, WORD INPUT LOADING, 3.5 us SETTLING TIME, 12-BIT DAC, PDSO20 |
| 封裝： | GREEN, PLASTIC, TSSOP-20 |
| 文件頁數： | 4/24頁 |
| 文件大小： | 463K |
| 代理商： | TLV5633IPWRG4 |
www.ti.com
DATA FORMAT
LAYOUT CONSIDERATIONS
SLAS190C – MARCH 1999 – REVISED SEPTEMBER 2006
The TLV5633 writes data either to one of the DAC holding latches or to the control register depending on the
address bits A1 and A0.
ADDRESS BITS
A1
A0
REGISTER
0
DAC LSW holding
0
1
DAC MSW holding
1
0
Reserved
1
Control
The following table lists the meaning of the bits within the control register.
D7
D6
D5
D4
D3
D2
D1
D0
X
REF1
REF0
RLDAC
PWR
SPD
X(1)
0(1)
(1)
Default values: X = Don't Care
SPD: Speed control bit
1
→ fast mode
0
→ slow mode
PWR: Power control bit
1
→ power down
0
→ normal operation
RLDAC: Load DAC latch
1
→ latch transparent 0 → DAC latch controlled by LDAC pin
REF1 and REF0 determine the reference source and the reference voltage.
REFERENCE BITS
REF1
REF0
REFERENCE
0
External
0
1
1.024 V
1
0
2.048 V
1
External
If an external reference voltage is applied to the REF pin, external reference must be selected.
To achieve the best performance, it is recommended to have separate power planes for GND, AVDD, and DVDD.
Figure 13 shows how to lay out the power planes for the TLV5633. As a general rule, digital and analog signals
should be separated as wide as possible. To avoid crosstalk, analog and digital traces must not be routed in
parallel. The two positive power planes (AVDD and DVDD) should be connected together at one point with a
ferrite bead.
A 100-nF ceramic low series inductance capacitor between DVDD and GND and a 1-F tantalum capacitor
between AVDD and GND placed as close as possible to the supply pins are recommended for optimal
performance.
12
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