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參數資料
| 型號： | TMC3503R2C50T |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | DAC |
| 英文描述： | PARALLEL, 8 BITS INPUT LOADING, 0.015 us SETTLING TIME, 8-BIT DAC, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數： | 12/17頁 |
| 文件大小： | 106K |
| 代理商： | TMC3503R2C50T |
TMC3503
PRODUCT SPECIFICATION
4
REV. 1.02 11/24/99
Pin Descriptions
Pin
Name
Pin Number
Value
Pin Function Description
LQFP
PLCC
Clock and Pixel I/O
CLK
26
27
TTL
Clock Input. The clock input is TTL-compatible and all pixel
data is registered on the rising edge of CLK. It is recommended
that CLK be driven by a dedicated TTL buffer to avoid reflection
induced jitter, overshoot, and undershoot.
R7-0
G7-0
B7-0
47-40
9-2
23-16
6-1, 44-43
14-7
25-18
TTL
Red, Green, and Blue Pixel Inputs. The R, G, and B digital
inputs are TTL-compatible and registered on the rising edge of
CLK.
Controls
SYNC
11
16
TTL
Sync Pulse Input. Bringing SYNC LOW, turns off a 40 IRE
(7.62 mA) current source which forms a sync pulse on any D/A
converter output connected to IOS. SYNC is registered on the
rising edge of CLK along with pixel data and has the same
pipeline latency as BLANK and pixel data. SYNC does not
override any other data and should be used only during the
blanking interval. If the system does not require sync pulses,
SYNC and IOS should be connected to GND.
BLANK
10
15
TTL
Blanking Input. When BLANK is LOW, pixel inputs are ignored
and the D/A converter outputs are driven to the blanking level.
BLANK is registered on the rising edge of CLK and has the
same two-pipe latency as SYNC and Data.
WHITE
—
26
TTL
Force Full Scale Input. When WHITE is HIGH, pixel inputs are
ignored and the D/A converter outputs are driven to their full-
scale output level. A BLANK input overwrites a WHITE input.
WHITE is register on the rising edge of CLK and has the same
two-pipe latency as SYNC and Data.
SLEEP
—
28
TTL
Power-down Control Input. When HIGH, SLEEP places the D/
A converter in a low-power-dissipation mode. The D/A current
sources and the digital processing are disabled. The last data
loaded into the input and D/A registers is retained. This control is
asynchronous.
Video Outputs
IOR
IOG
IOB
33
32
29
39
38
33
0.714 Vp-p
Red, Green, and Blue Data Outputs. The current source
outputs of the D/A converters are capable of driving RS-343A/
SMPTE-170M compatible levels into doubly-terminated 75 Ohm
lines. Sync pulses may be added to any D/A output.
IOS
32
(connected
to IOG)
37
0.714 Vp-p
SYNC Current Output. When this pin is connected to any of the
D/A converter outputs, a 40 IRE offset is added to the video
level. When the SYNC input is LOW, the current is turned off,
bring the sync tip voltage to 0.0V. If no sync pulse is required,
IOS should be grounded. When SYNC is HIGH, the current
flowing out of IOS is:
IOS = 3.64 (VREF / RREF)
Voltage Reference
VREF
35
41
+1.235 V
Voltage Reference Input/Output. An internal voltage source of
+1.235 Volts is output on this pin. An external +1.235 Volt
reference may be applied here which overrides the internal
reference. Decoupling VREF to GND with a 0.1F ceramic
capacitor is required.
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相關代理商/技術參數 |
參數描述 |
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| TMC3503R2C80 | 功能描述:數字化視頻/模擬轉換器集成電路 50Mhz Video D/a Conv Triple 8Bit RoHS:否 制造商:Texas Instruments 轉換器數量:3 輸出類型:Current 轉換速率:180 MSPs 分辨率:10 bit 接口類型:Parallel 電壓參考:Internal or External 積分非線性:- 2.5 LSB, 1.5 LSB 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:HTQFP 封裝:Tray |
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| TMC3521TT | 制造商:ADAM-TECH 制造商全稱:Adam Technologies, Inc. 功能描述:SCREW MACHINE SOCKETS & TERMINAL STRIPS |
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