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參數資料
| 型號： | TMDS361PAGR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | PLASTIC, TQFP-64 |
| 文件頁數： | 8/43頁 |
| 文件大小： | 2159K |
| 代理商： | TMDS361PAGR |
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V
CC
AV
CC
50 W
0.5pF
V
Y
V
Z
Y
Z
Driver
Receiver
D+
D–
V
ID
V
D+
V
D–
V
ID =V
– V
D+
D–
(V
+V
)
D+
D–
2
V
ICM =
V
OD =V – V
Y
Z
(V +V )
Y
Z
2
V
OC =
S0371-01
SLLS919A – DECEMBER 2008 – REVISED JANUARY 2009............................................................................................................................................ www.ti.com
SWITCHING CHARACTERISTICS (continued)
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
MAX
UNIT
AVCC = 3.3 V, RT = 50 , input TMDS clock
frequency = 225 MHz. See Figure 14for
measurement setup; residual jitter is the total
tJITC(PP)
Peak-to-peak output residual clock jitter
jitter measured at TTP4 minus the jitter
10
35
ps
measured at TTP1. See Figure 15 for the loss
profile of the cable used for tJITC(PP)
measurement.
tCLK1
Valid clock-detect enable time
AVCC = 3.3 V, RT = 50 , input TMDS clock
300
500
ns
frequency = 300 MHz. See Figure 13.
tCLK2
Invalid clock-detect disable time
AVCC = 3.3 V, RT = 50 , input TMDS clock
500
800
ns
frequency = 1 MHz. See Figure 13.
tSEL1
Port selection time (see (4)
AVCC = 3.3 V, RT = 50
300
500
ns
tSEL2
Port deselection time (see (5))
AVCC = 3.3 V, RT = 50
40
50
ns
fCD
Clock-detect frequency
25
300
MHz
(4)
tSEL1 includes the time for the valid clock detect enable time and tS1(HPD), because the tS1(HPD) event happens in parallel with tSEL1; thus,
the tSEL1 time is primarily the tCLK1 time.
(5)
tSEL2 is primarily the tS2(HPD) time.
Figure 9. TMDS Main-Link Test Circuit
16
Copyright 2008–2009, Texas Instruments Incorporated
Product Folder Link(s) :TMDS361
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