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參數資料
| 型號： | TMDS461PZIT |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封裝： | PLASTIC, TQFP-100 |
| 文件頁數： | 10/24頁 |
| 文件大小： | 1467K |
| 代理商： | TMDS461PZIT |
PRODUCTPREVIEW
APPLICATION INFORMATION
I
2C INTERFACE NOTES
SDA
SCL
Start
Condition
Stop
Condition
SDA
SCL
GENERAL I
2C PROTOCOL
SLLS915 – AUGUST 2008 ................................................................................................................................................................................................. www.ti.com
The I2C interface is used to access the internal registers of the TMDS461. I2C is a two-wire serial interface
developed by Philips Semiconductor, now NXP Semiconductors (see I2C-Bus Specification, Version 2.1, January
2000). The bus consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When the bus is idle,
both SDA and SCL lines are pulled high. All the I2C compatible devices connect to the I2C bus through open
drain I/O pins, SDA and SCL. A master device, usually a microcontroller or a digital signal processor, controls the
bus. The master is responsible for generating the SCL signal and device addresses. The master also generates
specific conditions that indicate the START and STOP of data transfer. A slave device receives and/or transmits
data on the bus under control of the master device. The TMDS461 works as a slave and supports the standard
mode transfer (100 kbps) and fast mode transfer (400 kbps) as defined in the I2C-Bus Specification. The
TMDS461 has been tested to be fully functional with the high-speed mode (3.4 Mbps) with an overall circuit load
of xxpf.
The basic access cycle consists of the following:
A start condition
A slave address cycle
Any number of data cycles
A stop condition
Figure 15. I2C Start and Stop Conditions
The master initiates data transfer by generating a start condition. The start condition is when a high-to-low
transition occurs on the SDA line while SCL is high, as shown in Figure 14. All I2C-compatible devices should
recognize a start condition.
The master then generates the SCL pulses and transmits the 7-bit address and the read/write direction bit
R/W on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition
requires the SDA line to be stable during the entire high period of the clock pulse (see Mechanical Data at
end of this data sheet). All devices recognize the address sent by the master and compare it to their internal
fixed addresses. Only the slave device with a matching address generates an acknowledge (see Figure 15)
by pulling the SDA line low during the entire high period of the ninth SCL cycle. On detecting this
acknowledge, the master knows that a communication link with a slave has been established.
The master generates further SCL cycles to either transmit data to the slave (R/W bit 0) or receive data from
the slave (R/W bit 1). In either case, the receiver needs to acknowledge the data sent by the transmitter. So
an acknowledge signal can either be generated by the master or by the slave, depending on which one is the
receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long
as necessary (See Figure 16).
To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low
to high while the SCL line is high (see Figure 14). This releases the bus and stops the communication link
with the addressed slave. All I2C compatible devices must recognize the stop condition. Upon the receipt of a
18
Copyright 2008, Texas Instruments Incorporated
Product Folder Link(s) :TMDS461
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