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參數資料
| 型號： | TMDS461PZIT |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封裝： | PLASTIC, TQFP-100 |
| 文件頁數： | 4/24頁 |
| 文件大小： | 1467K |
| 代理商： | TMDS461PZIT |
PRODUCTPREVIEW
TMDS DDC and Local I2C Pins
ELECTRICAL CHARACTERISTICS
SWITCHING CHARACTERISTICS
SLLS915 – AUGUST 2008 ................................................................................................................................................................................................. www.ti.com
detected by the sink micro-controller. An Interrupt Request occurs when any system level change is detected by
TMDS461, which is a change in 5V_PWR on the source side, a change in the selected port, or a change in the
selected port's valid clock detect. The micro-controller can read register address 0x01 to obtain the current status
of 5V_PWR, the selected port, and clock detect status. Once the micro-controller has read 0x01, the IRQ pin
returns to low.
It is desired that as soon as the sink mocro-controller gets an Interrupt Request, it reads register address 0x01.
GPIO mode: IRQ pin reflects the status of the selected port's clock detect. If a valid clock is detected by the clock
detect circuit, IRQ goes high. If no valid clock is detected, IRQ remains low.
When a TMDS port is selected the TMDS461 utilizes an I2C repeater improving signal performance. The
repeater is designed to isolate the parasitic effects of the system in order to aid with system level compliance.
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IL
Low input current
VCC = 3.6 V, VI = 0 V
10
A
Ilkg(Sink)
Input leakage current
Sink pins
VCC = 3.6 V, VI = 5.5 V
10
A
CIO(Sink)
Input/output capacitance
Sink pins
DC bias = 2.5 V, AC = 3.5 Vp-p,
15
pF
f = 100 kHz
VIH(Sink)
High-level input voltage
Sink pins
2.1
5.5
V
VIL1(Sink)
Low-level input voltage
Sink pins
OVS = HIGH
–0.2
0.4
V
VOL1(Sink)
Low-level output voltage
Sink pins
IO = 4 mA, OVS = HIGH
0.6
0.7
V
VIL2(Sink)
Low-level input voltage
Sink pins
OVS = LOW
–0.2
0.4
V
VOL2(Sink)
Low-level output voltage
Sink pins
IO = 4 mA, OVS = LOW
0.5
0.6
V
VIL3(Sink)
Low-level input voltage
Sink pins
OVS = HI-Z
–0.2
0.3
V
VOL3(Sink)
Low-level output voltage
Sink pins
IO = 4 mA, OVS = HI-Z
0.4
0.5
V
Ilkg(I2C)
Input leakage current
[1:4] Port pins
VCC = 3.6 V, VI = 5.5 V
TBD
A
CIO(I2C)
Input/Output capacitance
[1:4] Port pins
DC bias = 2.5 V, AC = 3.5 Vp-p,
15
pF
f = 100 kHz
VIH(I2C)
High-level input voltage
[1:4] Port pins
2.1
5.5
V
VIL(I2C)
Low-level input voltage
[1:4] Port pins
–0.2
1.5
V
VOL(I2C)
Low-level output voltage
[1:4] Port pins
IO = 4 mA
0.2
V
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tPLH1
Propagation delay time, low to high
Source to sink
204
459
ns
tPHL1
Propagation delay time, high to low
Source to sink
35
140
ns
tPLH2
Propagation delay time, low to high
Sink to source
194
351
ns
tPHL2
Propagation delay time, high to low
Sink to source
35
140
ns
tf1
Output signal fall time
Sink side
20
72
ns
tf2
Output signal fall time
Source side
20
72
ns
fSCL
SCL clock frequency for internal register
Local I2C
100
kHz
tW(L)
Clock LOW period for I2C register
Local I2C
4.7
s
tW(H)
Clock HIGH period for internal register
Local I2C
4
s
tSU1
Internal register setup time, SDA to SCL
Local I2C
250
ns
th(1)
*1
Internal register hold time, SCL to SDA
Local I2C
0
s
T(buf)
Internal register bus free time between STOP and START
Local I2C
4.7
s
12
Copyright 2008, Texas Instruments Incorporated
Product Folder Link(s) :TMDS461
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