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參數資料
| 型號： | TMDS461PZT |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封裝： | PLASTIC, TQFP-100 |
| 文件頁數： | 13/43頁 |
| 文件大小： | 3111K |
| 代理商： | TMDS461PZT |
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TMDS Main Link Pins
ELECTRICAL CHARACTERISTICS
SWITCHING CHARACTERISTICS
SLLS915 – JANUARY 2009 ............................................................................................................................................................................................... www.ti.com
The TMDS port of the TMDS461 is designed to be compliant with the Digital Video Interface (DVI) 1.0 and High
Definition Multimedia Interface (HDMI) 1.3a specifications. The differential output voltage swing can be fine-tuned
with the VSadj resistor.
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOH
Single-ended HIGH-level output voltage
AVCC – 10
AVCC + 10
mV
VOL
Single-ended LOW-level output voltage
AVCC –
mV
600
400
VSWING
Single-ended output voltage swing
400
600
mV
Change in steady-state common-mode output voltage
VOC(SS)
5
mV
between logic states
VOD(pp)
Peak-to-peak output differential voltage
800
1200
mV
V(O)SBY
Single-ended standby output voltage
AVCC – 10
AVCC + 10
mV
0 V
≤ VCC ≤ 1.5 V, AVCC = 3.3 V,
I(O)OFF
Single-ended power-down output current
–10
10
A
RT = 50
IOS
Short-circuit output current
See Figure 20
–15
12
15
mA
VCD(pp)
Minimum valid clock differential voltage (peak-to-peak)
Input TMDS clock frequency = 300 MHz
100
mV
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP(1)
MAX
UNIT
tPLH
Propagation delay time
250
800
ps
tPHL
Propagation delay time
250
800
ps
tR1
Rise time, fastest mode (default setting): Fastest
84
110
140
ps
Setting
tF1
Fall time, fastest mode (default setting): Fastest
84
110
140
ps
Setting
tR2
Rise time, fastest mode + 50 ps (approximately)
142
160
190
ps
tF2
Fall time, fastest mode + 50 ps (approximately)
142
160
190
ps
tR3
Rise time, fastest mode + 100 ps (approximately)
187
210
230
ps
tF3
Fall time, fastest mode + 100 ps (approximately)
187
210
230
ps
tR4
Rise time, fastest mode + 120 ps
216
230
260
ps
(approximately): Slowest Setting
tF4
Fall time, fastest mode + 120 ps (approximately):
216
230
260
ps
Slowest Setting
tSK(P)
Pulse skew (see (2))
8
15
ps
tSK(D)
Intra-pair skew
10
30
ps
tSK(O)
Inter-pair skew (see (3))
100
ps
tJITD(PP)
Peak-to-peak output residual data jitter
AVCC = 3.3 V, RT = 50 , dR = 2.25 Gbps.
40
88
ps
See Figure 18 for measurement setup;
residual jitter is the total jitter measured at
TTP4 minus the jitter measured at TTP1. See
Figure 19 for the loss profile of the cable used
length and input TMDS data rate.
(1)
All typical values are at 25°C and with a 3.3-V supply.
(2)
tsk(p) is the magnitude of the time difference between tPLH and tPHL of a specified terminal.
(3)
tsk(o) is the magnitude of the difference in propagation delay times between any specified terminals of a sink-port bank when inputs of
the active source port are tied together.
20
Copyright 2009, Texas Instruments Incorporated
Product Folder Link(s) :TMDS461
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