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參數資料
| 型號： | TMDS461PZTR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封裝： | PLASTIC, TQFP-100 |
| 文件頁數： | 10/43頁 |
| 文件大小： | 3111K |
| 代理商： | TMDS461PZTR |
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ELECTRICAL CHARACTERISTICS
SWITCHING CHARACTERISTICS
PULSE
GENERATOR
D.U.T.
VCC
5V
RT
VIN
VOUT
R =2k
L
W
C =100pF
L
SLLS915 – JANUARY 2009 ............................................................................................................................................................................................... www.ti.com
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IL
Low-level input current
VCC = 3.6 V, VI = 0 V
–10
10
A
Ilkg(Sink)
Input leakage current
Sink pins
VCC = 3.6 V, VI = 4.95 V
–10
10
A
CIO(Sink)
Input/output capacitance
Sink pins
DC bias = 2.5 V, AC = 3.5 Vp-p, f = 100 kHz
15
pF
VIH(Sink)
High-level input voltage
Sink pins
2.1
5.5
V
VIL1(Sink)
Low-level input voltage
Sink pins
OVS 1
–0.2
0.4
V
VOL1(Sink)
Low-level output voltage
Sink pins
IO = 3 mA, OVS = HIGH
0.6
0.7
V
VIL2(Sink)
Low-level input voltage
Sink pins
OVS 2
–0.2
0.4
V
VOL2(Sink)
Low-level output voltage
Sink pins
IO = 3 mA, OVS = LOW
0.5
0.6
V
VIL3(Sink)
Low-level input voltage
Sink pins
OVS 3
–0.2
0.3
V
VOL3(Sink)
Low-level output voltage
Sink pins
IO = 3 mA, OVS = high-Z
0.4
0.5
V
Ilkg(I2C)
Input leakage current
Port[1:4] pins
VCC = 3.6 V, VI = 4.95 V
–10
10
A
CIO(I2C)
Input/output capacitance
Port[1:4] pins
DC bias = 2.5 V, AC = 3.5 Vp-p, f = 100 kHz
15
pF
VIH(I2C)
High-level input voltage
Port[1:4] pins
2.1
5.5
V
VIL(I2C)
Low-level input voltage
Port[1:4] pins
–0.2
1.5
V
VOL(I2C)
Low-level output voltage
Port[1:4] pins
IO = 3 mA
0.2
V
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tPLH2
Propagation delay time, low to high
Source to sink
80
251
ns
tPHL2
Propagation delay time, high to low
Source to sink
35
200
ns
tPLH1
Propagation delay time, low to high
Sink to source
204
459
ns
tPHL1
Propagation delay time, high to low
Sink to source
35
200
ns
tf1
Output signal fall time
Sink side
20
72
ns
tf2
Output-signal fall time
Source side
20
72
ns
fSCL
SCL clock frequency for internal register
Local I2C
100
kHz
tW(L)
Clock LOW period for I2C register
Local I2C
4.7
s
tW(H)
Clock HIGH period for internal register
Local I2C
4
s
tSU1
Internal register setup time, SDA to SCL
Local I2C
250
ns
th(1)
*1
Internal register hold time, SCL to SDA
Local I2C
0
s
t(buf)
Internal register bus free time between STOP and START
Local I2C
4.7
s
tsu(2)
Internal register setup time, SCL to START
Local I2C
4.7
s
th(2)
Internal register hold time, START to SCL
Local I2C
4
s
tsu(3)
Internal register hold time, SCL to STOP
Local I2C
4
s
Figure 8. Sink-Side Test Circuit
18
Copyright 2009, Texas Instruments Incorporated
Product Folder Link(s) :TMDS461
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