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參數資料
| 型號： | TMP320C6211GJC167 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | TRIMMER, 1K |
| 中文描述： | 定點數字信號處理器 |
| 文件頁數： | 3/83頁 |
| 文件大小： | 1176K |
| 代理商： | TMP320C6211GJC167 |
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TMS320C6211, TMS320C6211B
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS073K
AUGUST 1998
REVISED MARCH 2004
3
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
description
The TMS320C62x
DSPs (including the TMS320C6211/C6211B devices) compose one of the fixed-point DSP
families in the TMS320C6000
DSP platform. The TMS320C6211 (C6211) and TMS320C6211B (C6211B)
devices are based on the high-performance, advanced VelociTI
very-long-instruction-word (VLIW)
architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for multichannel and
multifunction applications.
With performance of up to 1333 million instructions per second (MIPS) at a clock rate of 167 MHz, the
C6211/C6211B device offers cost-effective solutions to high-performance DSP programming challenges. The
C6211/C6211B DSP possesses the operational flexibility of high-speed controllers and the numerical capability
of array processors. This processor has 32 general-purpose registers of 32-bit word length and eight highly
independent functional units. The eight functional units provide six arithmetic logic units (ALUs) for a high
degree of parallelism and two 16-bit multipliers for a 32-bit result. The C6211/C6211B can produce two
multiply-accumulates (MACs) per cycle for a total of 333 million MACs per second (MMACS). The
C6211/C6211B DSP also has application-specific hardware logic, on-chip memory, and additional on-chip
peripherals.
The C6211/C6211B uses a two-level cache-based architecture and has a powerful and diverse set of
peripherals. The Level 1 program cache (L1P) is a 32-Kbit direct mapped cache and the Level 1 data cache
(L1D) is a 32-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 512-Kbit memory
space that is shared between program and data space. L2 memory can be configured as mapped memory,
cache, or combinations of the two.The peripheral set includes two multichannel buffered serial ports (McBSPs),
two general-purpose timers, a host-port interface (HPI), and a glueless external memory interface (EMIF)
capable of interfacing to SDRAM, SBSRAM and asynchronous peripherals.
The C6211/C6211B has a complete set of development tools which includes: a new C compiler, an assembly
optimizer to simplify programming and scheduling, and a Windows
debugger interface for visibility into source
code execution.
TMS320C6000 is a trademark of Texas Instruments.
Windows is a registered trademark of the Microsoft Corporation.
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