- 您現在的位置：買賣IC網 > PDF目錄382646 > TMP320C6211GJC167 (Texas Instruments, Inc.) TRIMMER, 1K PDF資料下載
參數資料
| 型號： | TMP320C6211GJC167 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | TRIMMER, 1K |
| 中文描述： | 定點數字信號處理器 |
| 文件頁數： | 37/83頁 |
| 文件大小： | 1176K |
| 代理商： | TMP320C6211GJC167 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁當前第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁
TMS320C6211, TMS320C6211B
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS073K
AUGUST 1998
REVISED MARCH 2004
37
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
power-supply sequencing
TI DSPs do not require specific power sequencing between the core supply and the I/O supply. However,
systems should be designed to ensure that neither supply is powered up for extended periods of time if the other
supply is below the proper operating voltage.
system-level design considerations
System-level design considerations, such as bus contention, may require supply sequencing to be
implemented. In this case, the core supply should be powered up at the same time as, or prior to (and powered
down after), the I/O buffers. This is to ensure that the I/O buffers receive valid inputs from the core before the
output buffers are powered up, thus, preventing bus contention with other chips on the board.
power-supply design considerations
For systems using the C6000
DSP platform of devices, the core supply may be required to provide in excess
of 2 A per DSP until the I/O supply is powered up. This extra current condition is a result of uninitialized logic
within the DSP(s) and is corrected once the CPU sees an internal clock pulse. With the PLL enabled, as the
I/O supply is powered on, a clock pulse is produced stopping the extra current draw from the supply. With the
PLL disabled, as many as five external clock cycle pulses may be required to stop this extra current draw. A
normal current state returns once the I/O power supply is turned on and the CPU sees a clock pulse. Decreasing
the amount of time between the core supply power up and the I/O supply power up can minimize the effects
of this current draw.
A dual-power supply with simultaneous sequencing, such as available with TPS563xx controllers or PT69xx
plug-in power modules, can be used to eliminate the delay between core and I/O power up [see the
Using the
TPS56300 to Power DSPs
application report (literature number SLVA088)]. A Schottky diode can also be used
to tie the core rail to the I/O rail, effectively pulling up the I/O power supply to a level that can help initialize the
logic within the DSP.
Core and I/O supply voltage regulators should be located close to the DSP (or DSP array) to minimize
inductance and resistance in the power delivery path. Additionally, when designing for high-performance
applications utilizing the C6000
platform of DSPs, the PC board should include separate power planes for
core, I/O, and ground, all bypassed with high-quality low-ESL/ESR capacitors.
相關PDF資料 |
PDF描述 |
|---|---|
| TMJ320C6211GJC167 | FIXED-POINT DIGITAL SIGNAL PROCESSORS |
| TMX320C6201GJC167 | FIXED-POINT DIGITAL SIGNAL PROCESSORS |
| TMX320C6211GNY167 | FIXED-POINT DIGITAL SIGNAL PROCESSORS |
| TMP320C6211GNY167 | FIXED-POINT DIGITAL SIGNAL PROCESSORS |
| TMJ320C6211GNY167 | FIXED-POINT DIGITAL SIGNAL PROCESSORS |
相關代理商/技術參數 |
參數描述 |
|---|---|
| TMP320C6211GJCA100 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:FIXED-POINT DIGITAL SIGNAL PROCESSOR |
| TMP320C6211GJL100 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:FIXED-POINT DIGITAL SIGNAL PROCESSOR |
| TMP320C6211GJL120 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:FIXED-POINT DIGITAL SIGNAL PROCESSOR |
| TMP320C6211GJL167 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:FIXED-POINT DIGITAL SIGNAL PROCESSORS |
| TMP320C6211GJLA100 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:FIXED-POINT DIGITAL SIGNAL PROCESSOR |
發布緊急采購，3分鐘左右您將得到回復。