
Device Configurations
47
April 2004
Revised May 2005
SPRS247E
Table 3
3. Peripheral Configuration (PERCFG) Register Selection Bit Descriptions
BIT
31:11
NAME
Reserved
DESCRIPTION
Reserved. Read-only, for proper device operation, all reserved bits have to be written with “0”.
Clocks and frame syncs select bits.
Determines which of the clock and frame sync pairs are input to McASP1.
00 =
ACLKR1, AFSR1 pins (default).
01 =
ACLKR1[1], AFSR1[1] pins
10 =
ACLKR1[2], AFSR1[2] pins
11 =
ACLKR1[3], AFSR1[3] pins
[designed for multiple non-simultaneous I2S sources with different clock sources].
10:9
AFCMUX[1:0]
8
MCASP1EN
McASP1 select bit.
Selects whether the McASP1 peripheral is enabled or disabled (default).
(This feature allows power savings by disabling the peripheral when not in use.)
0
=
McASP1 is disabled and the module is powered down [default].
1
=
McASP1 is enabled.
7
I2C1EN
Inter-integrated circuit 1 (I2C1) enable bit.
Selects whether I2C1 peripheral is enabled or disabled (default).
(This feature allows power savings by disabling the peripheral when not in use.)
0
=
I2C1 is disabled, and the module is powered down (default).
1
=
I2C1 is enabled.
6:4
Reserved
Reserved. Read-only, for proper device operation, all reserved bits have to be written with “0”.
Inter-integrated circuit 0 (I2C0) enable bit.
Selects whether I2C0 peripheral is enabled or disabled (default).
(This feature allows power savings by disabling the peripheral when not in use.)
0
=
I2C0 is disabled, and the module is powered down (default).
1
=
I2C0 is enabled.
3
I2C0EN
2
MCBSP1EN
McBSP1 enable bit.
This bit is read-only as a “1” (McBSP1 always enabled).
1
MCBSP0EN
McBSP0 enable bit .
This bit is read-only as a “1” (McBSP0 always enabled).
0
MCASP0EN
McASP0 select bit.
Selects whether the McASP0 peripheral is enabled or disabled.
(This feature allows power savings by disabling the peripheral when not in use.)
0
=
McASP0 is disabled.
1
=
McASP0 is enabled.