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參數(shù)資料
型號： TMP320C6413GTS500
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： Fixed-Point Digital Signal Processors
中文描述： 定點(diǎn)數(shù)字信號處理器
文件頁數(shù)： 91/140頁
文件大?。?/td> 1958K
代理商： TMP320C6413GTS500
Device Electrical Specifications
91
April 2004
Revised May 2005
SPRS247E
6
Parameter Information
Transmission Line
4.0 pF
1.85 pF
Z0 = 50
(see note)
Tester Pin Electronics
Data Sheet Timing Reference Point
Output
Under
Test
NOTE: The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects
must be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect.
The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer) from
the data sheet timings.
Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.
42
3.5 nH
Device Pin
(see note)
Figure 6
1. Test Load Circuit for AC Timing Measurements
The load capacitance value stated is only for characterization and measurement of AC timing signals. This
load capacitance value does not indicate the maximum load the device is capable of driving.
6.1
Signal Transition Levels
All input and output timing parameters are referenced to 1.5 V for both “0” and “1” logic levels.
V
ref
= 1.5 V
Figure 6
2. Input and Output Voltage Reference Levels for AC Timing Measurements
All rise and fall transition timing parameters are referenced to V
IL
MAX and V
IH
MIN for input clocks, V
OL
MAX
and V
OH
MIN for output clocks.
V
ref
= V
IL
MAX (or V
OL
MAX)
V
ref
= V
IH
MIN (or V
OH
MIN)
Figure 6
3. Rise and Fall Transition Time Voltage Reference Levels
6.2
Signal Transition Rates
All timings are tested with an input edge rate of 4 Volts per nanosecond (4 V/ns).
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