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參數資料
| 型號： | TMX320C6211BGHK167 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | MS3472W18-32P |
| 中文描述： | 定點數字信號處理器 |
| 文件頁數： | 36/83頁 |
| 文件大小： | 1176K |
| 代理商： | TMX320C6211BGHK167 |
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TMS320C6211, TMS320C6211B
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS073K
AUGUST 1998
REVISED MARCH 2004
36
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
Table 20. Characteristics of the Power-Down Modes
PRWD FIELD
(BITS 15
10)
POWER-DOWN
MODE
WAKE-UP METHOD
EFFECT ON CHIP’S OPERATION
000000
No power-down
—
—
001001
PD1
Wake by an enabled interrupt
CPU halted (except for the interrupt logic)
Power-down mode blocks the internal clock inputs at the
Power down mode blocks the internal clock inputs at the
boundary of the CPU, preventing most of the CPU’s logic from
switching. During PD1, EDMA transactions can proceed
between peripherals and internal memory.
010001
PD1
Wake by an enabled or
non-enabled interrupt
011010
PD2
Wake by a device reset
Output clock from PLL is halted, stopping the internal clock
structure from switching and resulting in the entire chip being
halted. All register and internal RAM contents are preserved. All
functional I/O “freeze” in the last state when the PLL clock is
turned off.
011100
PD3
Wake by a device reset
Input clock to the PLL stops generating clocks. All register and
internal RAM contents are preserved. All functional I/O “freeze” in
the last state when the PLL clock is turned off. Following reset, the
PLL needs time to re-lock, just as it does following power-up.
Wake-up from PD3 takes longer than wake-up from PD2 because
the PLL needs to be re-locked, just as it does following power-up.
—
All others
When entering PD2 and PD3, all functional I/O remains in the previous state. However, for peripherals which are asynchronous in nature or
peripherals with an external clock source, output signals may transition in response to stimulus on the inputs. Under these conditions,
peripherals will not operate according to specifications.
Reserved
—
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