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參數資料
| 型號： | TMX320C6211BGHK167 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | MS3472W18-32P |
| 中文描述： | 定點數字信號處理器 |
| 文件頁數： | 50/83頁 |
| 文件大小： | 1176K |
| 代理商： | TMX320C6211BGHK167 |
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TMS320C6211, TMS320C6211B
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS073K
AUGUST 1998
REVISED MARCH 2004
50
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
SYNCHRONOUS-BURST MEMORY TIMING
timing requirements for synchronous-burst SRAM cycles
(see Figure 20)
NO.
C6211
150
C6211
167
C6211BGFNA
150
C6211B
150
C6211B
167
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
6
t
su(EDV-EKOH)
Setup time, read EDx valid before
ECLKOUT high
2.5
2.5
2.5
ns
7
t
h(EKOH-EDV)
Hold time, read EDx valid after
ECLKOUT high
1
2.5
2
ns
The C6211/C6211B SBSRAM interface takes advantage of the internal burst counter in the SBSRAM. Accesses default to incrementing 4-word
bursts, but random bursts and decrementing bursts are done by interrupting bursts in progress. All burst types can sustain continuous data flow.
switching characteristics over recommended operating conditions for synchronous-burst SRAM
cycles
(see Figure 20 and Figure 21)
NO.
PARAMETER
C6211
150
C6211
167
C6211BGFNA
150
C6211B
150
C6211B
167
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
1
t
d(EKOH-CEV)
Delay time, ECLKOUT high to CEx
valid
1.5
6.5
1
6.5
1.2
6.5
ns
2
t
d(EKOH-BEV)
Delay time, ECLKOUT high to BEx
valid
6.5
6.5
6.5
ns
3
t
d(EKOH-BEIV)
Delay time, ECLKOUT high to BEx
invalid
1.5
1
1.2
ns
4
t
d(EKOH-EAV)
Delay time, ECLKOUT high to EAx
valid
6.5
6.5
6.5
ns
5
t
d(EKOH-EAIV)
Delay time, ECLKOUT high to EAx
invalid
1.5
1
1.2
ns
8
t
d(EKOH-ADSV)
Delay time, ECLKOUT high to
ARE/SDCAS/SSADS valid
1.5
6.5
1
6.5
1.2
6.5
ns
9
t
d(EKOH-OEV)
Delay time, ECLKOUT high to
AOE/SDRAS/SSOE valid
1.5
6.5
1
6.5
1.2
6.5
ns
10
t
d(EKOH-EDV)
Delay time, ECLKOUT high to EDx
valid
7
7
7
ns
11
t
d(EKOH-EDIV)
Delay time, ECLKOUT high to EDx
invalid
1.5
1
1.2
ns
12
t
d(EKOH-WEV)
Delay time, ECLKOUT high to
AWE/SDWE/SSWE valid
1.5
6.5
1
6.5
1.2
6.5
ns
The C6211/C6211B SBSRAM interface takes advantage of the internal burst counter in the SBSRAM. Accesses default to incrementing 4-word
bursts, but random bursts and decrementing bursts are done by interrupting bursts in progress. All burst types can sustain continuous data flow.
ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM
accesses.
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