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參數資料
| 型號： | TPS2346PWRG4 |
| 廠商： | Texas Instruments |
| 文件頁數： | 20/30頁 |
| 文件大小： | 490K |
| 描述： | IC HOT SWAP POWER MGR 24-TSSOP |
| 標準包裝： | 2,000 |
| 類型： | 熱交換控制器 |
| 應用： | 光纖學網絡（ONET） |
| 內部開關： | 無 |
| 電源電壓： | -5.2V，3.3V，5V，5.15V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 24-TSSOP |
| 包裝： | 帶卷 (TR) |
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TPS2346
SLUS529 MAY 2002
20
www.ti.com
APPLICATION INFORMATION
A turn-on sequence is initiated when the ENABLE
input is brought low (less than 0.8 V), assuming that all four
input supplies (at the VINx pins) are within their UV/OV tolerance windows. A voltage fault at any input supply
causes all loads to be held off. When ENABLE
is asserted, the Channel 1 amplifier is enabled, and a 58-礎
current source begins charging the IRAMP capacitor to generate the first IRAMP pulse. During the linear rising
edge portion of the IRAMP waveform, current is linearly ramped to the 5.15-V back-end plane. Once the voltage
at IRAMP reaches 1.5 V, the source is replaced with a 1.8-礎 sink that discharges IRAMP to 0 V. During this
discharge period, load charging current, if still required, is limited to IMAX, the current sense voltage (VMAX)
divided by the sense resistor value, R
SNSx
, or IMAXx = VMAXx / R
SNSx
, where x refers to any of the four
channels.
At the completion of the first pulse on IRAMP, the TPS2346 moves to the second voltage to be ramped up,
Channel 2, enables its LCA and begins generating the second pulse in the IRAMP train. At this time, fault
monitoring is enabled on the Channel 1 output. Therefore, if Channel 1 has failed to attain at least the
undervoltage threshold potential, a fault is detected, any active channels turned off, and the turn-on sequence
aborted. In this manner, the maximum time allowed for ramp-up of any of the channels is the duration of one
(1) IRAMP pulse. This protects against indefinite sourcing into faulted loads.The TPS2346 latches off in
response to faults, and can be reset either by toggling the ENABLE
input high and then low again, or by cycling
power to the device.
After the Channel 2 ramp pulse, the backend planes for Channel 3 and Channel 4 are ramped up in similar
fashion. Channel 2 fault detection is enabled at the start of the Channel 3 ramp pulse, and so on. Once all four
supplies are ramped up, Channel 4 fault detection is enabled on the fifth IRAMP pulse. This last pulse is of
relatively short duration, as charge and discharge currents of approximately 256 礎 are selected for the UV/OV4
enable pulse. If all four channels reach a known good state, the PG
output is asserted low.
Each load current waveform, at load turn-on, may have up to three distinct periods, as shown in Figure 20.
Initially after being enabled, the ramp generator output voltage is clamped to less than 100 mV. This results in
a corresponding clamp on load current of about 7% of the programmed IMAX value (with some variance due
to internal device offset). This temporary limit applies during approximately the first 500 祍 of output ramping
time. The purpose of this slow ramp period is to ensure the LCA is pulled out of saturation, and is closely tracking
the CS input, prior to enabling fast charging of the load. During this time, appreciable ramping of the back-end
voltage may or may not occur, depending on a number of factors including the IMAX value, the amount of bulk
capacitance on the load, and the magnitude and polarity of inherent offsets in the current control loop.
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