
TPS40020
TPS40021
TPS40022
SLUS535 – MARCH 2003
www.ti.com
7
APPLICATION INFORMATION
The TPS4002X series of devices are low-input voltage, synchronous, voltage mode-buck controllers. A typical
application circuit is shown in Figure 1. These controllers are designed to allow construction of
high-performance dc-to-dc converters with input voltages from 2.25 V to 5.5 V, and output voltages as low as
700 mV. Using a top side N-channel MOSFET for the primary buck switch results in lower switch resistance
for a given gate charge.
The device controls the delays from main switch off to rectifier turn on and from rectifier turn off to main switch
turn on in a way that minimizes diode losses (both conduction and recovery) in the synchronous rectifier. The
reduction in these losses is significant and can mean that for a given converter power level, smaller FETs can
be used, or that heat sinking can be reduced or even eliminated.
The controller provides for a coarse current-limit function that provides pulse-by-pulse current limiting, as well
as integrates overcurrent pulses to determine the existence of a persistant fault state at the converter output.
If a fault is detected, the converter shuts down for a period of time (determined by six soft-start cycles) and then
restarts. The current-limit threshold is adjustable with a single resistor connected from VDD to the ILIM/SYNC
pin. This overcurrent function is designed to protect against catastrophic faults only, and cannot be guaranteed
to protect against all overcurrent conditions.
The controller implements a closed-loop soft start function. Startup ramp time is set by a single external
capacitor connected to the SS pin. The SS pin also doubles as a shutdown function.
VOLTAGE REFERENCE
The bandgap cell is designed with a trimmed, curvature corrected (< 1%) 0.700-V output, allowing output
voltages as low as 700 mV to be obtained.
Oscillator
The ramp waveform is a saw-tooth form at the PWM frequency with a peak voltage of 1.25 V, and a valley of
0.3 V. The PWM duty cycle is limited to a maximum of 97%, allowing the bootstrap and charge pump capacitors
to charge during every cycle.
Bootstrap/Charge Pump
The TPS4002X series includes a charge pump to boost the drive voltage to the power MOSFET’s to higher
levels when the input supply is low. A capacitor connected from PVDD to PGND is the storage cap for the pump.
A capacitor connected from SW to BOOT2 gets charged every switching cycle while SW is low and its charge
is dumped on the PVDD capacitor when SW goes high. An internal switch disables the charge pump when the
voltage on PVDD reaches approximately 4.8 V and enables pumping when PVDD falls to approximately 4.6 V.
The high-side driver uses the capacitor from SW to BOOT1 as its power supply. When SW is low, this capacitor
charges from the PVDD capacitor. When the SW pin goes high, this capacitor provides above-rail drive for the
high-side N-channel FET.
Drivers
The HDRV and LDRV MOSFET drivers are capable of driving gate-to-source voltages up to 5.0 V. At 5 V VIN,
and using appropriate MOSFETs, a 20-A converter can be achieved. The LDRV driver switches between VDD
and ground, while the HDRV driver is referenced to SW and switches between BOOT1 and SW. The maximum
voltage between BOOT1 and SW is 5.0 V.