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| 型號(hào)： | TPS40101RGET |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 1.3 A SWITCHING CONTROLLER, 1000 kHz SWITCHING FREQ-MAX, PQCC24 |
| 封裝： | PLASTIC, QFN-24 |
| 文件頁(yè)數(shù)： | 20/37頁(yè) |
| 文件大小： | 774K |
| 代理商： | TPS40101RGET |
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Voltage Margining
Synchronization
Power Good Indication
SLUS726 – SEPTEMBER 2006
APPLICATION INFORMATION (continued)
The TPS40101 allows the user to make the output voltage temporarily be 3% above or below the nominal
output, or 5% above or below the nominal output. This is accomplished by connecting the MGU or MGD pins to
GND directly or through a resistance. See Table 1.
Table 1. Output Voltage Margining States
RESISTANCE TO GND (k
)
OUTPUT VOLTAGE
RMGU
RMGD
OPEN
Nominal
< 10
OPEN
+ 5%
OPEN
< 10
-5%
25 to 37
OPEN
+3%
OPEN
25 to 37
-3%
There are some important considerations when adjusting the output voltage.
Only one of these pins should be anything other than an open circuit at any given time. States not listed in
the table are invalid states and the behavior of the circuit may be erratic if this is tried.
When changing the output voltage using the margin pins, it is very important to let the margin transition
complete before altering the state of the margin pins again.
Do not use mechanical means (switches, non-wetted relay contacts, etc) to alter the margining state. The
contact bounce causes erratic behavior.
The TPS40101 may be synchronized to an external clock source that is faster than the free running frequency of
the circuit. The SYNC pin is a rising edge sensitive trigger to the oscillator that causes the current cycle to
terminate and starts the next switching cycle. It is recommended that the synchronization frequency be no more
than 120% of the free running frequency. Following this guideline leads to fewer noise and jitter problems with
the pulse width modulator in the device. The circuit can be synchronized to higher multiples of the free running
frequency, but be aware that this results in a proportional decrease in the amplitude of the ramp from the
oscillator applied to the PWM, leading to increased noise sensitivity and increased PWM gain, possibly affecting
control loop stability.
The pulse applied to the SYNC pin can be any duty ratio as long as the pulse either high or low is at least 100
ns wide. Levels are logic compatible with any voltage under 0.8 V considered a low and any voltage over 2 V
considered a high.
The PGD pin is an open drain output that actively pulls to GND if any of the following conditions are met
(assuming that the input voltage is above 4.5V)
Soft-start is active (VSS < 3.5 V)
Tracking is active (VTRKOUT > 0.7 V)
VFB < 0.61 V
VFB > 0.77 V
VUVLO < 1.33 V
Overcurrent condition exists
Die temperature is greater than 165
°C
A short filter (20
s) must be overcome before PGD pulls to GND from a high state to allow for short transient
conditions and noise and not indicate a power NOT good condition.
The PGD pin attempts to pull low in the absence of input power. If the VDD pin is open circuited, the voltage on
PGD typically behaves as shown in Figure 28.
27
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