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參數資料
| 型號： | TPS40101RGET |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 穩壓器 |
| 英文描述： | 1.3 A SWITCHING CONTROLLER, 1000 kHz SWITCHING FREQ-MAX, PQCC24 |
| 封裝： | PLASTIC, QFN-24 |
| 文件頁數： | 23/37頁 |
| 文件大小： | 774K |
| 代理商： | TPS40101RGET |
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ELECTRICAL CHARACTERISTICS
SLUS726 – SEPTEMBER 2006
-40
°C ≤ T
A = TJ≤ 85°C, VVDD = 12 V, RRT = 182 k, RGM = 232 k, RILIM = 121 k (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT VOLTAGE
VVDD
Operating range
4.5
18.0
V
OPERATING CURRENT
IDD
Quiescent current
VFB > 0.8 V, 0% duty cycle
1.3
1.8
2.5
mA
ISD
Shutdown current
VUVLO < 1 V
500
A
5VPB
7 V
≤ V
VDD≤ 18 V, 0 mA ≤ ILOAD≤ 30 mA
4.7
5.0
5.3
Internal regulator
V
4.5 V
≤ V
VDD < 7 V, 0 mA ≤ ILOAD≤ 30 mA
4.3
5.0
5.3
OSCILLATOR/RAMP GENERATOR
fSW
Programmable oscillator frequency
100
1000
kHz
4.5 V
≤ V
IN < 18 V,
fOSC
Oscillator frequency accuracy
250
275
300
-40
°C ≤ T
A = TJ≤ 125°C
VRAMP
Ramp amplitude(1)
0.5
VP-P
tOFF
Fixed off-time
100
150
ns
DMIN
Minimum duty cycle
0%
tMIN
Minimum controllable pulse width(1)
CLOAD = 4.7 nF, -40°C ≤ TA = TJ≤ 125°C
90
100
ns
VVLY
Valley voltage(1)
1.0
1.6
2.0
V
FREQUENCY SYNCHRONIZATION
VIH
High-level input voltage
2
V
VIL
Low-level input voltage
0.8
ISYNC
Input current, SYNC
VSYNC = 2.5 V
4.0
5.5
10.0
A
tSYNC
Mimimum pulse width, SYNC
50
ns
tSYNC_SH
Minimum set-up/hold time, SYNC(2)
100
SOFT-START AND FAULT IDLE
ISS
Soft-start source (charge) current
13
20
25
A
ISS_SINK
Soft-start sink (discharge) current
3.4
5.0
6.6
VSSC
Soft-start completed voltage
3.25
3.40
3.75
V
VSSD
Soft-start discharged voltage
0.15
0.20
0.25
Retry interval time to SS time ratio(1)
16
VSSOS
Offset from SS to error amplifier
300
500
800
mV
ERROR AMPLIFIER
GBWP
Gain bandwidth product(1)
3.5
5.0
MHz
AVOL
Open loop
60
80
dB
IBIAS
Input bias current, FB
50
200
nA
IOH
High-level output current
2
3
mA
IOL
Low-level output current
2
3
Slew rate(1)
2.1
V/
s
FEEDBACK REFERENCE
TA =TJ =25°C
686
690
694
VFB
Feedback voltage reference
mV
-40
°C < T
A = TJ≤ 125°C
683
697
(1)
Ensured by design. Not production tested.
(2)
To meet set up time requirements for the synchronization circuit, a negative logic pulse must be greater than 100 ns wide.
3
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