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參數資料
型號: TPS54010PWPG4
廠商: TEXAS INSTRUMENTS INC
元件分類: 穩壓器
英文描述: 25 A SWITCHING REGULATOR, 762 kHz SWITCHING FREQ-MAX, PDSO28
封裝: GREEN, PLASTIC, HTSSOP-28
文件頁數: 15/29頁
文件大小: 984K
代理商: TPS54010PWPG4
www.ti.com
DEAD-TIME CONTROL AND MOSFET
THERMAL SHUTDOWN
POWER-GOOD (PWRGD)
OVERCURRENT PROTECTION
TPS54010
SLVS509B – MAY 2004 – REVISED JUNE 2005
DRIVERS
The device uses the thermal shutdown to turn off the
Adaptive dead-time control prevents shoot-through
power MOSFETs and disable the controller if the
current
from
flowing
in
both
N-channel
power
junction temperature exceeds 150°C. The device is
MOSFETs during the switching transitions by actively
released from shutdown automatically when the junc-
controlling the turn-on times of the MOSFET drivers.
tion temperature decreases to 10°C below the ther-
The high-side driver does not turn on until the voltage
mal shutdown trip point, and starts up under control
at the gate of the low-side FET is below 2 V. While
of the slow-start circuit.
the low-side driver does not turn on until the voltage
Thermal shutdown provides protection when an over-
at the gate of the high-side MOSFET is below 2 V.
load condition is sustained for several milliseconds.
The high-side and low-side drivers are designed with
With a persistent fault condition, the device cycles
300-mA source and sink capability to quickly drive the
continuously; starting up by control of the slow-start
power MOSFETs gates. The low-side driver is sup-
circuit, heating up due to the fault condition, and then
plied from VIN, whereas the high-side driver is
shutting down on reaching the thermal shutdown trip
supplied from the BOOT pin. A bootstrap circuit uses
point. This sequence repeats until the fault condition
an external BOOT capacitor and an internal 2.5-
is removed.
bootstrap switch connected between the VIN and
BOOT pins. The integrated bootstrap switch improves
drive efficiency and reduces external component
The power-good circuit monitors for undervoltage
count.
conditions on VSENSE. If the voltage on VSENSE is
10% below the reference voltage, the open-drain
PWRGD output is pulled low. PWRGD is also pulled
The cycle-by-cycle current limiting is achieved by
low if VIN is less than the UVLO threshold or SS/ENA
sensing the current flowing through the high-side
is low. When VIN, UVLO threshold, SS/ENA, enable
MOSFET and comparing this signal to a preset
threshold,
and
VSENSE
>
90%
of
Vref,
the
overcurrent threshold. The high-side MOSFET is
open-drain output of the PWRGD pin is high. A
turned off within 200 ns of reaching the current limit
hysteresis voltage equal to 3% of Vref and a 35-s
threshold. A 100-ns leading-edge blanking circuit
falling-edge deglitch circuit prevent tripping of the
prevents current limit false tripping. Current limit
power-good comparator due to high-frequency noise.
detection occurs only when current flows from VIN to
PH when sourcing current to the output filter. Load
protection during current sink operation is provided by
thermal shutdown.
22
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