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參數資料
| 型號： | TPS54160DGQR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 穩壓器 |
| 英文描述： | 2.7 A SWITCHING REGULATOR, 2500 kHz SWITCHING FREQ-MAX, PDSO10 |
| 封裝： | GREEN, PLASTIC, MSOP-10 |
| 文件頁數： | 15/50頁 |
| 文件大小： | 1375K |
| 代理商： | TPS54160DGQR |
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RT / CLK
TPS54160
Clock
Source
PLL
R
fset
10pF
4kW
50 W
EXT
SLVS795C – OCTOBER 2008 – REVISED OCTOBER 2010
www.ti.com
DETAILED DESCRIPTION (continued)
How to Interface to RT/CLK Pin
The RT/CLK pin can be used to synchronize the regulator to an external system clock. To implement the
synchronization feature connect a square wave to the RT/CLK pin through the circuit network shown in
Figure 43. The square wave amplitude must transition lower than 0.5V and higher than 2.2V on the RT/CLK pin
and have an on time greater than 40 ns and an off time greater than 40 ns. The synchronization frequency range
is 100 kHz to 2200 kHz. The rising edge of the PH is synchronized to the falling edge of RT/CLK pin signal. The
external synchronization circuit should be designed in such a way that the device has the default frequency set
resistor connected from the RT/CLK pin to ground should the synchronization signal turn off. It is recommended
to use a frequency set resistor connected as shown in Figure 43 through a 50
resistor to ground. The resistor
should set the switching frequency close to the external CLK frequency. It is recommended to ac couple the
synchronization signal through a 10 pF ceramic capacitor to RT/CLK pin and a 4k
series resistor. The series
resistor reduces PH jitter in heavy load applications when synchronizing to an external clock and in applications
which transition from synchronizing to RT mode. The first time the CLK is pulled above the CLK threshold the
device switches from the RT resistor frequency to PLL mode. The internal 0.5V voltage source is removed and
the CLK pin becomes high impedance as the PLL starts to lock onto the external signal. Since there is a PLL on
the regulator the switching frequency can be higher or lower than the frequency set with the external resistor.
The device transitions from the resistor mode to the PLL mode and then will increase or decrease the switching
frequency until the PLL locks onto the CLK frequency within 100 microseconds.
When the device transitions from the PLL to resistor mode the switching frequency will slow down from the CLK
frequency to 150 kHz, then reapply the 0.5V voltage and the resistor will then set the switching frequency. The
switching frequency is divided by 8, 4, 2, and 1 as the voltage ramps from 0 to 0.8 volts on VSENSE pin. The
device implements a digital frequency shift to enable synchronizing to an external clock during normal startup
and fault conditions. Figure 44, Figure 45 and Figure 46 show the device synchronized to an external system
clock in continuous conduction mode (ccm) discontinuous conduction (dcm) and pulse skip mode (psm).
Figure 43. Synchronizing to a System Clock
22
Copyright 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): TPS54160
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