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參數資料
| 型號： | TPS65182BRGZT |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 電源管理 |
| 英文描述： | POWER SUPPLY SUPPORT CKT, PQCC48 |
| 封裝： | 7 X 7 MM, 0.9 MM, PLASTIC, QFP-48 |
| 文件頁數： | 5/24頁 |
| 文件大小： | 865K |
| 代理商： | TPS65182BRGZT |
www.ti.com
SLVSAA2C – MARCH 2010 – REVISED OCTOBER 2010
VPOS / VNEG SUPPLY TRACKING
LDO1 (VPOS) and LDO2 (VNEG) track each other in a way that they are of opposite sign but same magnitude.
The sum of VLDO1 and VLOD2 is guaranteed to be < 50 mV.
FAULT HANDLING AND RECOVERY
The TPS65182/TPS65182B monitors input and output voltages and die temperature and will take action if
operating conditions are outside normal limits. Whenever the TPS65182/TPS65182B encounters:
Thermal Shutdown (TSD)
Positive Boost Under Voltage (VB_UV)
Inverting Buck-Boost Under Voltage (VN_UV)
Input Under Voltage Lock Out (UVLO)
it will shut down all power rails and enter STANDBY mode. Shut down follows the pre-defined power-down
sequence and once a fault is detected, the PWR_GOOD pin is pulled low.
Whenver the TPS65182/TPS65182B encounters under voltage on VNEG (VNEG_UV), VPOS (VPOS_UV), VEE
(VEE_UV) or VDDH (VDDH_UV) it will shut down the corresponding rail (plus any dependent rail) only and
remain in ACTIVE mode, allowing the DCDC converters to remain up. Again, the PWR_GOOD pin will be pulled
low.
As the PWRx inputs are edge sensitive, the host must toggle the PWRx pins to re-enable the rails through GPIO
control, i.e. it must bring the PWRx pins low before asserting them again.
POWER GOOD PIN
The power good pin (PWR_GOOD) is an open drain output that is pulled high when all four power rails (CP1,
CP2, LDO1, LDO2) are in regulation and is pulled low if any of the rails encounters a fault. PWR_GOOD remains
low if one of the rails is not enabled by the host and only after all rails are in regulation PWR_GOOD is released
to HiZ state (pulled up by external resistor).
PANEL TEMPERATURE MONITORING
The TPS65182/TPS65182B provides circuitry to bias and measure an external negative temperature coefficient
resistor (NTC) to monitor device temperature in a range from –10°C to 85°C with and accuracy of ±1°C from 0°C
to 50°C. Temperature reading is automatically updated every 60 s.
NTC BIAS CIRCUIT
Figure 3 below shows the block diagram of the NTC bias and measurement circuit. The NTC is biased from an
internally generated 2.25-V reference voltage through an integrated 7.307-K
Ω bias resistor. A 43-KΩ resistor is
connected parallel to the NTC to linearize the temperature response curve. The circuit is designed to work with a
nominal 10-K
Ω NTC and achieves accuracy of ±1°C from 0°C to 50°C. The voltage drop across the NTC is
digitized by a 10-bit SAR ADC and translated into an 8-bit two’s complement by digital per Table 1.
Copyright 2010, Texas Instruments Incorporated
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