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參數資料
| 型號： | TS83102G0BMGS |
| 廠商： | ATMEL CORP |
| 元件分類： | ADC |
| 英文描述： | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CBGA152 |
| 封裝： | HERMATIC, CI-CGA-152 |
| 文件頁數： | 12/52頁 |
| 文件大小： | 1548K |
| 代理商： | TS83102G0BMGS |
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2
5360A–BDC–06/05
TS83102G0BMGS
1.
Description
The TS83102G0BMGS is a monolithic 10-bit analog-to-digital converter, designed for digitizing
wide bandwidth analog signals at very high sampling rates of up to 2 Gsps. It uses an innovative
architecture, including an on-chip Sample and Hold (S/H). The 3.3 GHz full power input band-
width and band flatness performances enable the digitizing of high IF and large bandwidth
signals.
Figure 1-1.
Simplified Block Diagram
2.
Functional Description
The TS83102G0BMGS is a 10-bit 2 Gsps ADC. The device includes a front-end master/slave
Track and Hold stage (Sample and Hold), followed by an analog encoding stage (Analog Quan-
tizer), which outputs analog residues resulting from analog quantization. Successive banks of
latches regenerate the analog residues into logical levels before entering an error correction cir-
cuit and resynchronization stage, followed by 50
differential output buffers.
The TS83102G0BMGS works in a fully differential mode from analog inputs to digital outputs. A
differential Data Ready output (DR/DRB) is available to indicate when the outputs are valid and
an Asynchronous Data Ready Reset ensures that the first digitized data corresponds to the first
acquisition.
The control pin B/GB (A11 of the CI-CGA package) is provided to select either a binary or gray
data output format. The gain control pin GA (R9 of the CI-CGA package) is provided to adjust
the ADC gain transfer function.
A Sampling Delay Adjust function (SDA) may be used to ease the interleaving of ADCs.
A pattern generator is integrated on the chip for debug or acquisition setup. This function is acti-
vated through the PGEB pin (A9 of the CI-CGA package).
An Out-of-range bit (OR/ORB) indicates when the input overrides 0.5 Vpp.
A selectable decimation by 32 functions is also available for enhanced testability coverage (A10
of the CI-CGA package), along with the die junction temperature monitoring function.
The TS83102G0BMGS uses only vertical isolated NPN transistors together with oxide isolated
polysilicon resistors, which allows enhanced radiation tolerance (over 100 kRad (Si) total dose
expected tolerance).
Sample &Hold
Clock generation
Logic block
Analog
Q
uant
izer
VIN
VINB
CLK
CLKB
PGEB
B/GB
DRRB
OR
ORB
D9
D9B
D0
D0B
GA
DR
DRB
50
SDA
DECB/
DIODE
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相關代理商/技術參數 |
參數描述 |
|---|---|
| TS83102G0BVGL | 制造商:e2v technologies 功能描述:ADC SGL 2GSPS 10-BIT PARALLEL 152CBGA - Trays |
| TS83102G0CGL | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog to Digital Converter |
| TS83102G0GSZR5 | 制造商:e2v technologies 功能描述:TS83102G0GSZR5 - Trays |
| TS831-3I | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:MICROPOWER VOLTAGE SUPERVISOR RESET ACTIVE LOW |
| TS831-3ID | 功能描述:監控電路 2.71V Micropower AL RoHS:否 制造商:STMicroelectronics 監測電壓數: 監測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復位:Resettable 監視器:No Watchdog 電池備用開關:No Backup 上電復位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
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