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參數資料
| 型號： | TS83102G0BMGS |
| 廠商： | ATMEL CORP |
| 元件分類： | ADC |
| 英文描述： | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CBGA152 |
| 封裝： | HERMATIC, CI-CGA-152 |
| 文件頁數： | 35/52頁 |
| 文件大小： | 1548K |
| 代理商： | TS83102G0BMGS |
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40
5360A–BDC–06/05
TS83102G0BMGS
9.6
Digital Outputs: Termination and Logic Compatibility
Each single-ended output of the TS83102G0BMGS’s differential output buffers are internally
50
terminated, and feature a 100 differential output impedance. The 50 resistors are con-
nected to the VPLUSD digital power supply. The TS83102G0BMGS output buffers are designed
to drive 50
controlled impedance lines properly terminated by a 50 resistor. A 10.5 mA bias
current flowing alternately into one of the 50
resistors when switching, ensures a 0.25V
single-ended voltage drop across the resistor (0.5V differential).
Each single-ended output transmission line length must be kept identical (< 3 mm). Mismatches
in the differential line lengths may cause variations in the output differential common mode.
It is recommended to bypass the midpoint of the differential 100
termination with a 47 pF
capacitor, so as to avoid common mode perturbations in case of a slight mismatch in the differ-
ential output line lengths.
See the recommended termination scenarios in Figures 46. and 47. below.
Note:
Since the output buffers feature a 100
differential output impedance, it is possible to directly
drive high the input impedance storing registers without terminating the 50
transmission lines.
Timewise, this means that the incident wave reflects at the 50
transmission line output and trav-
els back to the 50
data output buffer. Since the buffer output impedance is 50, no
back reflection occurs and the output swing is doubled.
9.6.0.1
VPLUSD Digital Power Supply Settings
For differential ECL digital output levels: V
PLUSD should be supplied with -0.8V (or connected
to ground via a 5
resistor to ensure the -0.8 voltage drop).
For the LVDS digital output logic compatibility: V
PLUSD should be tied to 1.45V
(±75 mV).
If used with the TS81102G0 DMUX, V
PLUSD can be set to ground.
9.6.1
ECL Differential Output Termination Configurations
Figure 9-7.
50
Terminated Differential Outputs (Recommended)
10.5 mA
Zc = 50
OUT
VPLUSD = -0.8 V
Zc = 50
50
50
OUTB
50
50
VOL typ = -1.17 V
VOH typ = -0.94 V
Differential Output Swing:
±0.23 V = 0.46 Vpp
Common Mode Level = -1.05 V
47 pF
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相關代理商/技術參數 |
參數描述 |
|---|---|
| TS83102G0BVGL | 制造商:e2v technologies 功能描述:ADC SGL 2GSPS 10-BIT PARALLEL 152CBGA - Trays |
| TS83102G0CGL | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog to Digital Converter |
| TS83102G0GSZR5 | 制造商:e2v technologies 功能描述:TS83102G0GSZR5 - Trays |
| TS831-3I | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:MICROPOWER VOLTAGE SUPERVISOR RESET ACTIVE LOW |
| TS831-3ID | 功能描述:監控電路 2.71V Micropower AL RoHS:否 制造商:STMicroelectronics 監測電壓數: 監測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復位:Resettable 監視器:No Watchdog 電池備用開關:No Backup 上電復位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
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