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參數資料
| 型號： | TS83102G0BMGS |
| 廠商： | ATMEL CORP |
| 元件分類： | ADC |
| 英文描述： | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CBGA152 |
| 封裝： | HERMATIC, CI-CGA-152 |
| 文件頁數： | 30/52頁 |
| 文件大小： | 1548K |
| 代理商： | TS83102G0BMGS |
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36
5360A–BDC–06/05
TS83102G0BMGS
The DRRB’s rising edge occurs when the external encoding clock input (CLK/CLKB) is HIGH
: the Data Ready output’s first rising edge occurs after one clock period on the clock’s falling
edge, and a TDR delay time of 410 ps.
Consequently, as the analog input is sampled on the clock’s rising edge, the first digitized data
corresponding to the first acquisition (N), after a Data Ready signal restart (rising edge), is
always strobed by the third rising edge of the Data Ready signal.
The time delay (TD1) is specified between the last point of a change in the differential output
data (zero crossing point) to the rising or falling edge of the differential Data Ready signal
(DR/DRB) [zero crossing point].
Note:
For normal initialization of the Data Ready output signal, the external encoding clock signal fre-
quency and level must be controlled. The minimum encoding clock sampling rate for the ADC is
150 Msps, due to the internal Sample and Hold drop rate. Consequently the clock cannot be
stopped.
9.2.3
Timing Diagram
Figure 9-1.
TS83102G0BMGS Timing Diagram (2 Gsps Clock Rate) - Data Ready Reset Clock Held at LOW Level
Figure 9-2.
TS83102G0BMGS Timing Diagram (2 Gsps Clock Rate) - Data Ready Reset Clock Held at HIGH Level
N - 4
N - 3
N - 2
N - 1
N
N + 1
VIN/VINB
CLK/CLKB
Digital
Outputs
Data Ready
DR/DRB
Data Ready
Reset
TA = 160 ps
N
N + 1
N + 2
N + 3
N - 5
TOD = 360 ps
TDR = 410 ps
TRDR = 1000 ps
1 ns
TC = 500 ps
TC1 TC2
TPD = 4.0 Clock Period
TOD = 360 ps
500 ps
TDR = 410 ps
TD1 = TC1 + TDR - TOD
= TC1 + 50 ps = 300 ps
TD2 = TC2 + TOD - TDR
= TC2 - 50 ps = 200 ps
N - 4
N - 3
N - 2
N - 1
N
N + 1
N - 5
500 ps
TD2 = TC2 + TOD - TDR
= TC2 - 50 ps = 200 ps
TD1 = TC1 + TDR - TOD
= TC1 + 50 ps = 300 ps
TDR = 410 ps
TPD = 4.0 Clock Periods
TOD = 360 ps
TRDR = 1000 ps
1 ns
TDR = 410 ps
TOD = 360 ps
TA = 160 ps
N
N + 1
N + 2
N + 3
TC = 500 ps
TC1
TC2
VIN/VINB
CLK/CLKB
Digital
Outputs
Data Ready
DR/DRB
Data Ready
Reset
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