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參數(shù)資料
| 型號： | TS83102G0BVGL |
| 廠商： | E2V TECHNOLOGIES PLC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CBGA152 |
| 封裝： | 21 X 21 MM, 1.27 MM PITCH, CERAMIC, BGA-152 |
| 文件頁數(shù)： | 39/60頁 |
| 文件大小： | 1510K |
| 代理商： | TS83102G0BVGL |
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44
0830E–BDC–06/07
TS83102G0B
e2v semiconductors SAS 2007
13.6.3
LVDS Logic Compatibility
Figure 13-11. LVDS Format (Refer to the IEEE Standards 1596.3 - 1994): 1125 mV < Common Mode
<1275 mV and 250 mV < Output Swing < 400 mV
13.7
Main Functions of the ADC
13.7.1
Out-of-range Bit (OR/ORB)
The out-of-range bit reaches a logical high state when the input exceeds the positive full-scale or falls
below the negative full-scale. When the analog input exceeds the positive full-scale, the digital outputs
remain at a logical high state with OR/ORB at a logical one. When the analog input falls below the nega-
tive full-scale, the digital outputs remain at a logical low state, with OR/ORB at a logical one again.
13.7.2
Bit Error Rate (BER)
The TS83102G0B’s internal regeneration latches indecisions (for inputs very close to the latches’ thresh-
old). This may produce errors in the logic encoding circuitry, leading to large amplitude output errors.
This is because the latches regenerate the internal analog residues into logical states with a finite volt-
age gain value (Av) within a given positive amount of time D(t): Av = exp (D (t)/t), with t being the positive
regeneration time constant feedback.
The TS83102G0B has been designed to reduce the probability of such errors occuring to
10-12 (measured for the converter at 2 Gsps). A standard technique for reducing the amplitude of such
errors down to ±1 LSB consists in setting the digital output data to gray code format. However, the
TS83102G0B has been designed to feature a Bit Error Rate of 10-12 with a binary output format.
13.7.3
Gray or Binary Output Data Format Selection
To reduce the amplitude of such errors when they occur, it is possible to choose between the binary or
gray output data format by storing gray output codes.
Digital data format selection:
BINARY output format if B/GB is floating or GND.
GRAY output format if B/GB is connected to V
EE.
13.7.4
Pattern Generator Function
The pattern generator function (enabled by connecting pin A9 PGEB to V
EE = -5V) allows you to rapidly
check the ADC’s operation thanks to a checker board pattern delivered internally to the ADC. Each of
Common Mode
(Each Single-ended Output
Swing Max
Voh Max = 1.575V
Swing Min
Voh Min
= 1.575V
Vol Max
= 1.075V
Vol Min = 0.825V
CM Max
= 1275 mV
CM Min
= 1125 mV
Output Swing Max = ±300 mVp
Output Swing Min = ±200 mVp
0V
True-False Output
False-True Output
Swing Max
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TS83102G0CGL | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog to Digital Converter |
| TS83102G0GSZR5 | 制造商:e2v technologies 功能描述:TS83102G0GSZR5 - Trays |
| TS831-3I | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:MICROPOWER VOLTAGE SUPERVISOR RESET ACTIVE LOW |
| TS831-3ID | 功能描述:監(jiān)控電路 2.71V Micropower AL RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數(shù): 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| TS831-3IDT | 功能描述:監(jiān)控電路 2.71V Micropower AL RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數(shù): 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
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