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參數資料
| 型號： | TS8388BCFS |
| 廠商： | E2V TECHNOLOGIES PLC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68 |
| 封裝： | CERAMIC, QFP-68 |
| 文件頁數： | 27/62頁 |
| 文件大小： | 1267K |
| 代理商： | TS8388BCFS |
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33
0860E–BDC–05/07
e2v semiconductors SAS 2007
TS8388B
8.4.3
Single-ended ECL Clock Input
In single-ended configuration enter on CLK (resp. CLKB) pin, with the inverted phase clock input pin
CLKB (respectively CLK) connected to –1.3V through the 50
termination resistor.
The inphase input amplitude is 1V peak to peak, centered on –1.3V common mode.
Figure 8-5.
Single-ended Clock Input (ECL):
VCLK Common Mode = –1.3V; VCLKB = –1.3V
8.5
Noise Immunity Information
Circuit noise immunity performance begins at design level.
Efforts have been made on the design in order to make the device as insensitive as possible to chip
environment perturbations resulting from the circuit itself or induced by external circuitry (Cascode
stages isolation, internal damping resistors, clamps, internal (on-chip) decoupling capacitors).
Furthermore, the fully differential operation from analog input up to the digital outputs provides enhanced
noise immunity by common mode noise rejection.
Common mode noise voltage induced on the differential analog and clock inputs will be canceled out by
these balanced differential amplifiers.
Moreover, proper active signals shielding has been provided on the chip to reduce the amount of cou-
pled noise on the active inputs.
The analog inputs and clock inputs of the TS8388B device have been surrounded by ground pins, which
must be directly connected to the external ground plane.
8.6
Digital Outputs
The TS8388B differential output buffers are internally 75
loaded. The 75 resistors are connected to
the digital ground pins through a –0.8V level shift diode (see Figure 8-6, Figure 8-7, Figure 8-8 on page
36).
The TS8388B output buffers are designed for driving 75
(default) or 50 properly terminated imped-
ance lines or coaxial cables. An 11 mA bias current flowing alternately into one of the 75
resistors
when switching ensures a 0.825V voltage drop across the resistor (unterminated outputs).
The V
PLUSD positive supply voltage allows the adjustment of the output common mode level from –1.2V
(V
PLUSD = 0V for ECL output compatibility) to +1.2V (VPLUSD = 2.4V for LVDS output compatibility).
Therefore, the single-ended output voltages vary approximately between –0.8V and –1.625V, (outputs
unterminated), around –1.2V common mode voltage.
Three possible line driving and back-termination scenarios are proposed (assuming V
PLUSD = 0V):
-1.8V
-0.8V
t
[V]
VCLK
VCLKB = -1.3V
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