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參數資料
| 型號： | TS8388BCFS |
| 廠商： | E2V TECHNOLOGIES PLC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68 |
| 封裝： | CERAMIC, QFP-68 |
| 文件頁數： | 28/62頁 |
| 文件大小： | 1267K |
| 代理商： | TS8388BCFS |
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34
0860E–BDC–05/07
TS8388B
e2v semiconductors SAS 2007
1.
75
impedance transmission lines, 75 differentially terminated (Figure 8-6):
Each output voltage varies between –1V and –1.42V (respectively +1.4V and +1V), leading to
±
0.41V = 0.825V in differential, around –1.21V (respectively +1.21V) common mode for V
PLUSD = 0V
(respectively 2.4V).
2.
50
impedance transmission lines, 50 differentially termination (Figure 8-7):
Each output voltage varies between –1.02V and –1.35V (respectively +1.38V and +1.05V), leading
to ±0.33V = 660 mV in differential, around –1.18V (respectively +1.21V) common mode for V
PLUSD =
0V (respectively 2.4V).
3.
75
impedance open transmission lines (Figure 8-8):
Each output voltage varies between –1.6V and –0.8V (respectively +0.8V and +1.6V), which are true
ECL levels, leading to ±0.8V = 1.6V in differential, around –1.2V (respectively +1.2V) common mode
for V
PLUSD = 0V (respectively 2.4V). Therefore, it is possible to drive directly high input impedance
storing registers, without terminating the 75
transmission lines. In time domain, that means that the
incident wave will reflect at the 75
transmission line output and travel back to the generator (that is:
the 75
data output buffer). As the buffer output impedance is 75, no back reflection will occur.
Note: This is no longer true if a 50
transmission line is used, as the latter is not matching the buffer 75
output impedance.
Each differential output termination length must be kept identical. It is recommended to decouple the
midpoint of the differential termination with a 10 nF capacitor to avoid common mode perturbation in
case of slight mismatch in the differential output line lengths.
Too large mismatches (keep < a few mm) in the differential line lengths will lead to switching currents
flowing into the decoupling capacitor leading to switching ground noise.
The differential output voltage levels (75
or 50 termination) are not ECL standard voltage levels, how-
ever it is possible to drive standard logic ECL circuitry like the ECLinPS logic line from Freescale.
At sampling rates exceeding 1 Gsps, it may be difficult to trigger any Acquisition System with digital out-
puts. It becomes necessary to regenerate digital data and Data Ready by means of external amplifiers,
in order to be able to test the TS8388B at its optimum performance conditions.
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| TS8388BCF | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68 |
| TS8388BVF | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68 |
| TS8388BMFB/Q | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68 |
| TS8388BMF | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68 |
| TS8388BCG | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CBGA72 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| TS8388BCG | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:A/D CONVERTER |
| TS8388BCGL | 制造商:e2v technologies 功能描述:ADC 8-BIT 1 GSPS - Trays |
| TS8388BCGL (+LID) | 制造商:e2v technologies 功能描述:ADC 8-BIT 1 GSPS - Trays |
| TS8388BMF | 制造商:e2v technologies 功能描述:ADC 8-BIT 1 GSPS - Trays |
| TS8388BMFB/Q | 制造商:e2v technologies 功能描述:ADC 8-BIT 1 GSPS - Trays |
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