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參數(shù)資料
型號(hào)： TS8388BMFSB/Q
廠商： E2V TECHNOLOGIES PLC
元件分類： ADC
英文描述： 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68
封裝： CERAMIC, QFP-68
文件頁(yè)數(shù)： 5/62頁(yè)
文件大小： 1267K
代理商： TS8388BMFSB/Q
13
0860E–BDC–05/07
e2v semiconductors SAS 2007
TS8388B
Note:
1. The common mode level of the output buffers is 1.2V below the positive digital supply.
For ECL compatibility the positive digital supply must be set at 0V (ground).
For LVDS compatibility (output common mode at +1.2V) the positive digital supply must be set at 2.4V.
If the subsequent LVDS circuitry can withstand a lower level for input common mode, it is recommended to lower the positive
digital supply level in the same proportion in order to spare power dissipation.
B0B, B1B, B2B, B3B,
B4B, B5B, B6B, B7B
B7, B8, B9, C11, G10, H10, L10, L9
Inverted phase (-) digital outputs.
B0B is the inverted LSB. B7B is the inverted MSB.
OR
K7
In phase (+) Out of Range Bit. Out of Range is high on the
leading edge of code 0 and code 256.
ORB
L8
Inverted phase (+) Out of Range Bit (OR).
DR
E10
In phase (+) output of Data Ready Signal.
DRB
D11
Inverted phase (-) output of Data Ready Signal (DR).
GORB
A7
Gray or Binary select output format control pin.
- Binary output format if GORB is floating or VCC.
- Gray output format if GORB is connected at ground (0V).
GAIN
K6
ADC gain adjust pin. The gain pin is by default grounded, the
ADC gain transfer function is nominally close to one.
DIOD/DRRB
K1
Die function temperature measurement pin and
asynchronous data ready reset active low, single-ended ECL
input.
V
PLUSD
B11, C10, J10, K11
+2.4V for LVDS output levels otherwise to GND(2).
NC
A1, A11, L1, L11
Not connected.
Table 6-1.
TS8388BGL Pin Description (CBGA68 Package)
Symbol
Pin number
Function
相關(guān)PDF資料
PDF描述
TS8388BVF 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68
TS8388BMFS9NC3 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68
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