- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄98299 > TS8388BMFSB/Q (E2V TECHNOLOGIES PLC) 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68 PDF資料下載
參數(shù)資料
| 型號： | TS8388BMFSB/Q |
| 廠商： | E2V TECHNOLOGIES PLC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68 |
| 封裝： | CERAMIC, QFP-68 |
| 文件頁數(shù)： | 62/62頁 |
| 文件大小： | 1267K |
| 代理商： | TS8388BMFSB/Q |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁當(dāng)前第62頁
9
0860E–BDC–05/07
e2v semiconductors SAS 2007
TS8388B
3. Histogram testing based on sampling of a 10 MHz sinewave at 50 Msps.
4. Output error amplitude < ± 4 lsb around correct code (including gain and offset error).
5. Maximum jitter value obtained for single-ended clock input on the JTS8388B die (chip on board): 200 fs. (500 fs expected on
TS8388BG)
6. Digital output back termination options depicted in Application Notes.
7. With a typical value of TD = 465 ps, at 1 Gsps, the timing safety margin for the data storing using the ECLinPS 10E452 out-
put registers from Freescale is of ± 315 ps, equally shared before and after the rising edge of the Data Ready signals (DR,
DRB).
8. The clock inputs may be indifferently entered in differential or single-ended, using ECL levels or 4 dBm typical power level
into the 50
termination resistor of the inphase clock input. (4 dBm into 50 clock input correspond to 10 dBm power level
for the clock generator.)
9. At 1 Gsps, 50/50 clock duty cycle, TC2 = 500 ps (TC1). TDR - TOD = –100 ps (typ) does not depend on the sampling rate.
10. Specified loading conditions for digital outputs:
- 50
or 75 controlled impedance traces properly 50/75 terminated, or unterminated 75 controlled impedance traces.
- Controlled impedance traces far end loaded by 1 standard ECLinPS register from Freescale. (that is: 10E452) (Typical
input parasitic capacitance of 1.5 pF including package and ESD protections.)
11. Termination load parasitic capacitance derating values:
- 50
or 75 controlled impedance traces properly 50/75 terminated: 60 ps/pF or 75 ps per additional ECLinPS load.
- Unterminated (source terminated) 75
controlled impedance lines: 100 ps/pF or 150 ps per additional ECLinPS termina-
tion load.
12. Apply proper 50/75
impedance traces propagation time derating values: 6 ps/mm (155 ps/inch) for TSEV8388B Evaluation
Board.
13. Values for TOD and TDR track each other over temperature, (1% variation for TOD-TDR per 100
°C temperature variation).
Therefore TOD-TDR variation over temperature is negligible. Moreover, the internal (on-chip) and package skews between
each Data TODs and TDR effect can be considered as negligible. Consequently, minimum values for TOD and TDR are
never more than 100 ps apart. The same is true for the TOD and TDR maximum values (see Advanced Application Notes
14. Min value guarantees performance. Max value guarantees functionality.
15. Min value guarantees functionality. Max value guarantees performance.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TS8388BVF | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68 |
| TS8388BMFS9NC3 | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68 |
| TS8388BCGL | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CBGA68 |
| TS8388BMFS | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68 |
| TS8388BVGL | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CBGA68 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TS8388BVF | 制造商:e2v technologies 功能描述:ADC 8-BIT 1 GSPS - Trays |
| TS8388BVFS | 制造商:e2v technologies 功能描述:ADC 8-BIT 1 GSPS - Trays |
| TS8388BVGL | 制造商:e2v technologies 功能描述:ADC 8-BIT 1 GSPS - Trays |
| TS8388BVGL (+LID) | 制造商:e2v technologies 功能描述:ADC 8-BIT 1 GSPS - Trays |
| TS83C194 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Microcontroller |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。