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參數資料
| 型號： | TSA5526M |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | XO, clock |
| 英文描述： | ELECTRICAL POWER CORD |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 1300 MHz, PDSO16 |
| 封裝： | 4.40 MM, PLASTIC, SSOP-16 |
| 文件頁數： | 8/28頁 |
| 文件大小： | 290K |
| 代理商： | TSA5526M |
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1996 Sep 24
8
Philips Semiconductors
Product specification
1.3 GHz universal bus-controlled
TV synthesizers
TSA5526; TSA5527
Table 6
Test bits
T2
T1
T0
TSA5526; TSA5527
TSA5526A; TSA5527A
REMARKS
0
0
0
normal operation with automatic
charge-pump switch ON
normal operation with automatic
charge-pump switch OFF
charge-pump is OFF
charge-pump is sinking current
charge-pump is sourcing current
f
ref
is available at LOCK output
automatic charge-pump switch OFF
0
0
1
automatic charge-pump switch ON
status at POR
0
1
1
1
1
1
1
0
X
0
1
0
charge-pump is OFF
charge-pump is sinking current
charge-pump is sourcing current
f
ref
is available at LOCK output
the ADC cannot be used
when test mode is active
the ADC cannot be used
when test mode is active
1
0
1
1
2
f
div
is available at LOCK output
1
2
f
div
is available at LOCK output
Table 7
Ratio select bits
R
EAD MODE
(R/W =
LOGIC
1); see Table 8
Data can be read from the device by setting the R/W bit to
logic 1. After the slave address has been recognized, the
device generates an acknowledge pulse and the first data
byte (status byte) is transferred on the SDA line (MSB
first). Data is valid on the SDA line during a HIGH level of
the SCL clock signal. A second data byte can be read from
the device if the microcontroller generates an
acknowledge on the SDA line (master acknowledge).
End of transmission will occur if no master acknowledge
occurs.
RSA
RSB
REFERENCE DIVIDER
X
0
1
0
1
1
640
1024
512
The device will then release the data line to allow the
microcontroller to generate a stop condition. The POR flag
is set to logic 1 at power-on. The flag is reset when an
end-of-data is detected by the device (end of a read
sequence). Control of the loop is made possible with the
in-lock flag (FL) which indicates when the loop is locked
(FL = logic 1).
The Automatic Charge-Pump Switch flag (ACPS) is LOW
when the automatic charge-pump switch mode is ON and
the loop is locked. In other conditions ACPS = logic 1.
When ACPS = logic 0, the charge-pump current is forced
to the LOW value.
A built-in ADC is available at pin 12 (I
2
C-bus only).
This converter can be used to apply AFC information to the
microcontroller from the IF section of the television.
The relationship between the bits A2 to A0 is given in
Table 9.
Table 8
Read data format
Notes
1.
2.
3.
4.
5.
A = acknowledge.
POR = power-on reset flag (POR = logic 1 at power-on).
FL = in-lock flag (FL = logic 1 when the loop is locked).
ACPS = automatic charge-pump switch flag (active ACPS = logic 0; non-active ACPS = logic 1).
A2 to A0 = digital outputs of the 5-level ADC.
BYTE
MSB
DATA BYTE
LSB
SLAVE
ANSWER
A
(1)
Address Byte (ADB)
Status Byte (SB)
1
1
0
0
1
0
1
MA1
A2
(5)
MA0
A1
(5)
R/W = 1
A0
(5)
POR
(2)
FL
(3)
ACPS
(4)
相關PDF資料 |
PDF描述 |
|---|---|
| TSA5526T | ELECTRICAL POWER CORD |
| TSA5527AM | 1.3 GHz universal bus-controlled TV synthesizers |
| TSA5527AT | 1.3 GHz universal bus-controlled TV synthesizers |
| TSB12LV32-EP | IC APEX 20KE FPGA 100K 324-FBGA |
| TSB12LV01B-EP | FPGA (Field-Programmable Gate Array) |
相關代理商/技術參數 |
參數描述 |
|---|---|
| TSA5526T | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1.3 GHz universal bus-controlled TV synthesizers |
| TSA5526TD-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:I2C-Bus Frequency Synthesizer |
| TSA5527 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1.3 GHz universal bus-controlled TV synthesizers |
| TSA5527AM | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1.3 GHz universal bus-controlled TV synthesizers |
| TSA5527AT | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1.3 GHz universal bus-controlled TV synthesizers |
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