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參數資料
| 型號： | TSC2302IRGZRG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC48 |
| 封裝： | GREEN, PLASTIC, VQFN-48 |
| 文件頁數： | 24/85頁 |
| 文件大小： | 1483K |
| 代理商： | TSC2302IRGZRG4 |
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TSC2302
SLAS394 – JULY 2003
Secondary Configuration Register (Page 1, Address 06H):
This register allows the user to read the status of the DAV pin through the SPI interface. It also controls the audio
codec PLL.
BIT 15
BIT 14
BIT 13
BIT 12
BIT 11
BIT 10
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
MSB
LSB
SDAV
RESV
PLLO
PCTE
PDC3
PDC2
PDC1
PDC0
A3
A2
A1
A0
N3
N2
N1
N0
Bit 15 — SDAV (read only)
SPI Data Available. This read-only bit mirrors the function of the DAV pin. This bit is provided so that the host
processor can poll the SPI interface to see whether data is available, without dedicating a GPIO pin from the host
processor to the TSC2302 DAV pin. This bit is normally high, goes low when touch screen or keypad data is
available, and is reset high when all the new data has been read. When written to, this bit becomes KBC1,
operation detailed below.
Table 19. SPI Data Available (Read Only)
SDAV
DESCRIPTION
0
Touchscreen data is available.
1
No new data available (default)
Bit 13 — PLLO
PLL Output on GPIO_0. This bit allows the user to receive the output of the audio codec internal PLL. This bit is
provided so the host processor can use the output of the PLL, to generate its I2S signals in sync with an external
MCLK or crystal oscillator. Writing a 0 to this bit connects the output of the PLL to the GPIO_0 pin. Otherwise,
the GPIO_0 pin operates as normal.
Table 20. PLL Output
PLLO
DESCRIPTION
0
Output PLL on GPIO_0.
1
GPIO_0 operates as normal (default).
Bit 12 — PCTE
PLL Control Enable. This bit allows the user to manually control the audio codec internal PLL. This allows the
user to modify the contents of bits [11-0] to control the audio codec PLL. Writing a 0 to this bit enables manual
control of the PLL. Otherwise, the PLL is set automatically based on the settings of MCLK [1:0] and I2SFS[3:0] in
the audio control register (bits 7-2 in register 00h, page 2).
Table 21. PLL Control Enable
PLLO
DESCRIPTION
0
Allows modification of bits [11:0].
1
PLL operates as normal, no manual override (default).
30
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