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參數資料
| 型號： | TSC2302IRGZRG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC48 |
| 封裝： | GREEN, PLASTIC, VQFN-48 |
| 文件頁數： | 65/85頁 |
| 文件大小： | 1483K |
| 代理商： | TSC2302IRGZRG4 |
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TSC2302
SLAS394 – JULY 2003
Bits [1:0] — I2SFM1-I2SFM0
I2S Format. These two bits select the I2S interface format. Both 16-bit and 20-bit data formats are supported. The
default format is 20-bit I2S.
Table 31. I2S Format Selection
I2SFM [1:0]
I2SFM1
I2SFM0
DESCRIPTION
0
DAC: 16-bit, MSB-first, right justified ADC: 16-bit, MSB-first, left justified
0
1
DAC: 20-bit, MSB-first, right justified ADC: 20-bit, MSB-first, left justified
1
0
DAC: 20-bit, MSB-first, left justified ADC: 20-bit, MSB-first, left justified
1
DAC: 20-bit, MSB-first, I2S (default) ADC: 20-bit, MSB-first, I2S (default)
ADC VOLUME CONTROL REGISTER (Page 2, Address 01h)
The ADC volume control register controls the independent programmable gain amplifiers (PGA’s) on the left and
right channel inputs to the audio ADCs of the TSC2302. The gain of these PGAs can be adjusted from
-40 dB to +20 dB in 0.5-dB steps. The ADC inputs can also be hard-muted, or internally shorted to VCM so that
no input signal is seen.
The ADC volume control register is formatted as follows:
BIT 15
BIT 14
BIT 13
BIT 12
BIT 11
BIT 10
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
MSB
LSB
ADMUL
ADVL6
ADVL5
ADVL4
ADVL3
ADVL2 ADVL1 ADVL0
ADMUR
ADVR6
ADVR5
ADVR4
ADVR3
ADVR2
ADVR
1
0
Bit 15 — ADMUL
Left ADC Mute. This bit is used to mute the input to the left channel ADC volume control. The user can set this
bit to mute the ADC while retaining the previous gain setting in ADVL[6:0], so that the PGA returns to the
previous gain setting when ADMUL is cleared. When the ADMUL bit is set, the left ADC PGA soft-steps down to
its lowest level, then mutes. This procedure is used to reduce any audible artifacts (pops or clicks) during the
mute operation. This soft-stepping process is reversed when the ADMUL bit is cleared (unmute).
Table 32. Left ADC Mute
ADMUL
DESCRIPTION
0
Left channel ADC is active.
1
Left channel ADC is mute. (default)
Bits [14:8] — ADVL6- ADVL0
Left ADC Volume Control. These 7 bits control the gain setting of the left channel ADC volume control. This
volume control can be programmed from -40 dB to +20 dB in 0.5-dB steps. Full volume (+20 dB) corresponds to
a setting of 7Fh. Unity gain (0 dB) corresponds to 57h. Full attenuation (-40 dB) corresponds to 07h. Any value
lower than 07h engages the mute function described above. Volume control changes are always soft-stepped, as
described above. The default volume setting is 0 dB.
ADVL[6:0] = 1010111 (087d) = 0 dB (default)
ADVL[6:0] = 1111111 (127d) = +20 dB (Max)
ADVL[6:0] = 0000111 (007d) = -40 dB (Min)
ADVL[6:0] = 0d-6d = mute
68
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