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參數資料
| 型號： | TSL3301CL |
| 廠商： | AMS-TAOS USA Inc |
| 文件頁數： | 3/21頁 |
| 文件大?。?/td> | 659K |
| 描述： | IC LINEAR SENSOR ARRAY 8CHIPLED |
| 標準包裝： | 1 |
| 系列： | * |
| 其它名稱： | TSL3301-CLDKR |
TSL3301CL
102 ?1 LINEAR OPTICAL SENSOR ARRAY
WITH ANALOG-TO-DIGITAL CONVERTER
TAOS141 JULY 2011
2
r
r
Copyright E 2011, TAOS Inc.
The LUMENOLOGY r Company
www.taosinc.com
Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
GND
6, 7
Ground
SCLK
1
I
System clock input for serial I/O and all internal logic.
SDIN
3
I
Serial data input. Data is clocked in on the rising edge of SCLK.
SDOUT
4
O
Serial data output. Data is clocked out on the falling edge of SCLK.
V
DD
2
Positive supply voltage.
Detailed Description
The TSL3301CL is a 102 ?1 linear optical array with onboard A/D conversion. It communicates over a serial
digital interface and operates over a 3 V to 5.5 V range. The array is divided into three 34-pixel zones (left, center,
and right), with each zone having programmable gain and offset (dark signal) correction.
The sensor consists of 102 photodiodes, also called pixels, arranged in a linear array. Light energy impinging
on a pixel generates a photocurrent, which is then integrated by the active integration circuitry associated with
that pixel. During the integration period, a sampling capacitor connects to the output of the integrator through
an analog switch. The amount of charge accumulated at each pixel is directly proportional to the light intensity
(E
e
) on that pixel and to the integration time (t
int
). At maximum programmed gain, one LSB corresponds to
approximately 300 electrons.
Integration, sampling, output, and reset of the integrators are performed by the control logic in response to
commands input via the SDIN pin. Data is read out on the SDOUT pin. A normal sequence of operation consists
of a pixel reset (RESET), start of integration (STARTInt), integration period, sampling of integrators
(SAMPLEInt), and pixel output (READPixel). Reset sets all the integrators to zero. Start of integration releases
the integrators from the reset state and defines the beginning of the integration period. Sampling the integrators
ends the integration period and stores the charge accumulated in each pixel in a sample and hold circuit.
Reading the pixels causes the sampled value of each pixel to be converted to 8-bit digital format and output on
the SDOUT pin. All 102 pixels are output sequentially unless interrupted by an abort (ABORTPixel) command
or reset by a RESET command.
Gain adjustment is controlled by three 5-bit DACs, one for each of the the three zones. Table 1 lists the gain
settings and the corresponding pixel values. Offset is affected by the gain setting and may have to be adjusted
after gain changes are made.
Offset correction is controlled by three 8-bit sign-magnitude
DACs and is performed in the analog domain prior
to the digital conversion. There is a separate offset DAC for each of the three zones. Codes 0h 7Fh correspond
to positive offset values and codes 80h FFh correspond to negative offset values.
The offset correction is proportional to the gain setting. At minimal gain, one LSB of the offset DAC corresponds
to approximately 1/3 LSB of the device output, and at maximum gain, to about 1 LSB of the device output.
Note that the gain and offset registers are in indeterminate states after power up and must be set by the controller
as required.
Sign-magnitude is a binary representation in which the most significant bit (MSB) is used to represent the sign of the number, with the
remaining bits representing the magnitude. An MSB of 1 indicates a negative number.
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