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參數資料
| 型號： | TSL3301CL |
| 廠商： | AMS-TAOS USA Inc |
| 文件頁數： | 5/21頁 |
| 文件大小： | 659K |
| 描述： | IC LINEAR SENSOR ARRAY 8CHIPLED |
| 標準包裝： | 1 |
| 系列： | * |
| 其它名稱： | TSL3301-CLDKR |
TSL3301CL
102 ?1 LINEAR OPTICAL SENSOR ARRAY
WITH ANALOG-TO-DIGITAL CONVERTER
TAOS141 JULY 2011
4
r
r
Copyright E 2011, TAOS Inc.
The LUMENOLOGY r Company
www.taosinc.com
Register Address Map
The TSL3301CL contains seven registers as defined in Table 2. Data in these registers may be written to or read
from using the REGWrite and REGRead commands. Three registers control the gain of the analog-to-digital
converters (ADC). Three other registers allow the offset of the system to be adjusted. Together the gain and
offset registers are used to maximize the achievable dynamic range.
Table 2. Register Address Map
ADDRESS
REGISTER DESCRIPTION
REGISTER WIDTH
0x00
Left (pixels 033) offset
8
0x01
Left (pixels 033) gain
5
0x02
Center (pixels 3467) offset
8
0x03
Center (pixels 3467) gain
5
0x04
Right (pixels 68101) offset
8
0x05
Right (pixels 68101) gain
5
0x1F
Mode
8
The offset registers are 8-bit sign-magnitude values and the gain registers are 5-bit values. The programmed
offset correction is applied to the sampled energy, and then the gain is applied. (i.e., the gain will affect the offset
correction.) These registers allow the user to maximize the dynamic range achievable in the given system.
The last register is the mode register. Bits in this register select the sleep mode as well as options for multichip
arrays and production testing. Note that test and multichip options do not apply to the 8-pin packaged device.
Users should always write 0s into the production test and multichip control bits.
0
7
0x1F
6
5
4
3
2
1
P2
MODE
0
0
SLP
P1
P0
C1
C0
SLP = Sleep Mode:
1 places device into sleep mode
0 places device in normal operating mode
C1, C0 are Reserved (should be written 0)
P2 to P0 are factory test bits (should be written 0)
Figure 1. Mode Register Bit Assignments
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