
U6268B
TELEFUNKEN Semiconductors
Rev. A1, 21-May-97
Preliminary Information
4 (12)
logic data transmission from the external unit to the inter-
face is completed.
CLLx is the output stage of a comparator with an internal
threshold and with the OCMx input. A OCMx-voltage
higher than 2.4 V creates a logic low at CLLx, and a
OCMx-voltage lower than 1.43 V creates a logic high at
CLLx. The comparator has an internal hysteresis with
typically 0.4 V.
With the pull-down resistor R
OCMx
= 750 at OCMx, the
correct OUTx-current threshold related to the logical out-
put CLLx is ensured. The CLLx is ’low’ if the
OUTx-current is higher than 27.3 mA, and the CLLx is
’high’, if the OUTx-current is lower than 19.1 mA. The
comparator has an internal hysteresis of typically 5 mA.
The tolerance of the R
OCM
resistor is assumed to be 0%.
The CLL-pin is an open-collector output and needs a
pull-up resistor of typically 2 k to the 5-V supply. For
ESD protection, a 7-V Zener diode is implemented.
RETURN 1, RETURN 2
The RETURNx pin provides a low-ohmic connection to
GND via a switched open-collector NPN-transistor. If
ENABLEx is high, RETURNx is switched on with a satu-
ration voltage less than 0.5 V at I
RETURNx
ENABLEx is low or open, RETURNx is a current sink
with
2 mA. RETURNx is current-limited at typically
150 mA.
50 mA. If
SC
The smooth capacitor is designed to realize the long-time
constant for the slow voltage change at OUTx for both in-
terface channels. The capacity is typ. 22 nF. At the rising
edge of V
Batt
, the maximum slew rate is V
OUTx
= 5 V/ms,
and at the falling edge of V
Batt
, the maximum slew rate
is V
OUTx
= 10 V/ms.
GND-Pins
By means of a GND bond from the chip to Pin 1 and Pin 8,
high ground breakage security is achieved and lowest
voltage drop and ground shift between IC- and circuit
ground is provided. The four GND pins and the die pad
are directly connected to the copper leadframe, resulting
in a very low thermal resistance, R
thJC
. In order to achieve
a good thermal resistance, R
thJA,
a good copper connec-
tion from the four GND pins to the metal parts of the
modul housing is also recommended.
Power Dissipation
Worst case calculation of the supply current I
S
:
I
S
= 1,278
( I
OUT1
+ I
OUT2
) + 18 mA
Worst case calculation of the IC’s power dissipation P
V
:
P
V
= (V
S
I
S
) – [(V
S
– V
diff
– V
ret-sat
)
+R
OCM
((I
OUT12
+ I
OUT22
) / 81)]
(I
OUT1
+ I
OUT2
)
V
S
voltage difference V
S
to V
OUTx
V
diff
= 3.6 at 12 V
V
diff
= 0.8 at 5.7 V
V
ret-sat
= 0.5 V saturation voltage return
I
OUTx
= output current at Pin OUTx = 0 to 60 mA
R
OCM
= resistor at Pin OCMx
= supply voltage 5.7 to 25 V
V
S
V
S
25 V
8.5 V
Selective Overtemperature Protection
An overtemperature protection is integrated which gene-
rates a switch-off signal at a chip temperature of typically
T
j
= 160
°
C and a switch-on signal at typically T
j
= 150
°
C.
In case of a detected overtemperature, only the corre-
sponding channel is disabled. The other channel stays
enabled.
The RETURNx is switched off if the voltage at RE-
TURNx is higher than 2 V (short-circuit comparator
threshold) and overtemperature is detected.
The OUTx is switched off if the voltage at OCMx is
higher than 4.6 V (overcurrent detection level) and over-
temperature is detected. The OCM voltage monitors the
output current at OUTx via the current ratio of 0.1. The
overcurrent-detection level of OUTx can be varied by
changing the OCMx resistor. If OUTx is switched off by
overtemperature and overcurrent detection, the CLLx
output remains logic low (overcurrent).
As the IC is only overtemperature-protected for short-cir-
cuit conditions at RETURNx or OUTx, it has to be
checked in each application that the chip temperature
does not exceed T
jmax
= 150
°
C in normal operation.
Test Hint
The overtemperature signal can be activated by con-nect-
ing ENABLE1 or ENABLE2 to 9 V/ 10 mA.